CYNSE70256-66BHC Cypress Semiconductor Corp, CYNSE70256-66BHC Datasheet - Page 84

• Manufacturer Part Number: CYNSE70256-66BHC
• Manufacturer: Cypress Semiconductor Corp

Specifications of CYNSE70256-66BHC

• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Package Type: BGA
• Mounting: Surface Mount
• Lead Free Status / Rohs Status: Not Compliant

The Learn operation lasts two CLK cycles. The sequence of operation is as follows.
At the end of cycle 2, a new instruction can begin. SRAM Write latency is the same as the Search to the SRAM Read cycle. It is
measured from the second cycle of the Learn instruction.
11.0
The NSE application can depth-cascade the devices to various table sizes of different widths (72 bits, 144 bits, or 288 bits). The
devices perform all the necessary arbitration to decide which device will drive the SRAM bus. Search latency increases as the
table size increases; the Search rate itself remains constant.
11.1
Figure 11-1 shows that up to four devices can be cascaded to form 512K × 72, 256K × 144, or 128K × 288 tables. It also shows
the interconnection between devices for depth cascading. Each NSE asserts the LHO[1] and LHO[0] signals to inform
downstream devices of its result. LHI[6:0] signals for a device are connected to LHO signals of the upstream devices. The host
ASIC must program the TLSZ to 01 for each of up to four devices in a block. Only a single device drives the SRAM bus in any
single cycle.
11.2
Figure 11-2 shows the cascading of up to four blocks. Each block except the last contains up to four CYNSE70256 devices, and
the interconnection within each with the cascading of up to four devices in a block was shown in the previous subsection.
Note:
Document #: 38-02035 Rev. *E
30. The interconnection between blocks for depth cascading is important. For each Search, a block asserts BHO[2], BHO[1], and BHO[0]. The BHO[2:0] signals for
• Cycle 1A: The host ASIC applies the Learn instruction on CMD[1:0] using CMDV = 1. The CMD[5:2] field specifies the index
• Cycle 1B: The host ASIC continues to drive CMDV to 1, CMD[1:0] to 11, and CMD[5:2] with the comparand pair index. CMD[6]
• Cycle 2: The host ASIC drives CMDV to 0.
of the comparand register pair that will be written in the data array in the 144-bit-configured table. For a Learn in a 72-bit-
configured table, the even-numbered comparand specified by this index will be written. CMD[8:6] carries the bits that will be
driven on SADR[23:21] in the SRAM Write cycle.
must be set to 0 if the Learn is being performed on a 72-bit-configured table, and to 1 if the Learn is being performed on a
144-bit-configured table.
a block are taken only from the last device in that block. For all other devices within that block, these signals stay open and floating. The host ASIC must program
TLSZ to 10 in each of the devices for cascading up to fifteen devices (in up to four blocks).
CMDV
CMD[10:0]
SSF, SSV
DQ[71:0]
Depth Cascading up to Four Devices (One Block)
Depth Cascading up to Fifteen Devices (Four Blocks)
Depth Cascading
Figure 11-1. Hardware Diagram for a Block of up to Four Devices
BHI[2:0]
BHI[2:0]
BHI[2:0]
BHI[2:0]
CYNSE70256 #2
CYNSE70256 #3
CYNSE70256 #0
CYNSE70256 #1
0
0
0
0
LHO[1]
LHO[1]
1
1
1
1
LHO[1]
2
2
2
2
LHI
LHI
LHI
LHI
LHO[1]
LHO[0]
3
3
3
3
LHO[0]
4
4
4
4
LHO[0]
5
5
5
5
LHO[0]
6
6
6
6
CYNSE70256
BHO[0]
BHO[1]
BHO[2]
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SRAM
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