DSPB56364FU100 Freescale Semiconductor, DSPB56364FU100 Datasheet - Page 10

• Manufacturer Part Number: DSPB56364FU100
• Manufacturer: Freescale Semiconductor

Specifications of DSPB56364FU100

• Device Core Size: 24b
• Format: Fixed Point
• Clock Freq (max): 100MHz
• Mips: 100
• Device Input Clock Speed: 100MHz
• Ram Size: 9KB
• Program Memory Size: 24KB
• Operating Supply Voltage (typ): 3.3V
• Operating Supply Voltage (min): 3.14V
• Operating Supply Voltage (max): 3.46V
• Operating Temp Range: -40C to 105C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 100
• Package Type: LQFP
• Lead Free Status / Rohs Status: Not Compliant

Interrupt and Mode Control
2.6
The interrupt and mode control signals select the chip’s operating mode as it comes out of hardware reset.
After RESET is deasserted, these inputs are hardware interrupt request lines.
2-6
MODD/
Signal Name
MODA/
MODB/
RESET
IRQA
IRQB
IRQD
Interrupt and Mode Control
Type
Input
Input
Input
Input
State During
Reset
Input
Input
Input
Input
Table 2-8 Interrupt and Mode Control
DSP56364 Technical Data, Rev. 4.1
Mode Select A/External Interrupt Request A—MODA/
Schmitt-trigger input, internally synchronized to the internal system clock.
MODA/
becomes a level-sensitive or negative-edge-triggered, maskable interrupt request
input during normal instruction processing. MODA, MODB, and MODD select one
of 8 initial chip operating modes, latched into the OMR when the
is deasserted. If
multiple processors can be re synchronized using the WAIT instruction and
asserting
and
This input is 5 V tolerant.
Mode Select B/External Interrupt Request B—MODB/
Schmitt-trigger input, internally synchronized to the internal system clock.
MODB/
becomes a level-sensitive or negative-edge-triggered, maskable interrupt request
input during normal instruction processing. MODA, MODB, and MODD select one
of 8 initial chip operating modes, latched into OMR when the
deasserted. If
multiple processors can be re-synchronized using the WAIT instruction and
asserting
This input is 5 V tolerant.
Mode Select D/External Interrupt Request D—MODD/
Schmitt-trigger input, internally synchronized to the internal system clock.
MODD/
becomes a level-sensitive or negative-edge-triggered, maskable interrupt request
input during normal instruction processing. MODA, MODB, and MODD select one
of 8 initial chip operating modes, latched into OMR when the
deasserted. If
multiple processors can be re synchronized using the WAIT instruction and
asserting
This input is 5 V tolerant.
Reset—
is placed in the reset state and the internal phase generator is reset. The
Schmitt-trigger input allows a slowly rising input (such as a capacitor charging) to
reset the chip reliably. When the
operating mode is latched from the MODA, MODB, and MODD inputs. The
RESET
be supplied before deassertion of
This input is 5 V tolerant.
IRQA
IRQA
IRQB
IRQD
RESET
signal must be asserted during power up. A stable EXTAL signal must
IRQA
IRQB
IRQD
is asserted, the processor will exit the stop state.
selects the initial chip operating mode during hardware reset and
selects the initial chip operating mode during hardware reset and
IRQB
selects the initial chip operating mode during hardware reset and
IRQD
to exit the wait state. If the processor is in the stop standby state
IRQA
to exit the wait state.
to exit the wait state.
is an active-low, Schmitt-trigger input. When asserted, the chip
is asserted synchronous to the internal system clock,
is asserted synchronous to the internal system clock,
is asserted synchronous to the internal system clock,
Signal Description
RESET
RESET
signal is deasserted, the initial chip
.
Freescale Semiconductor
IRQA
IRQB
IRQD
RESET
RESET
is an active-low
is an active-low
is an active-low
RESET
signal is
signal is
signal