DSPB56364FU100 Freescale Semiconductor, DSPB56364FU100 Datasheet - Page 65

DSPB56364FU100

Manufacturer Part Number
DSPB56364FU100
Description
Manufacturer
Freescale Semiconductor
Datasheet

Specifications of DSPB56364FU100

Device Core Size
24b
Format
Fixed Point
Clock Freq (max)
100MHz
Mips
100
Device Input Clock Speed
100MHz
Ram Size
9KB
Program Memory Size
24KB
Operating Supply Voltage (typ)
3.3V
Operating Supply Voltage (min)
3.14V
Operating Supply Voltage (max)
3.46V
Operating Temp Range
-40C to 105C
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Pin Count
100
Package Type
LQFP
Lead Free Status / Rohs Status
Not Compliant

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Freescale Semiconductor
1
2
3
4
5
6
7
No.
459
460
461
462
463
464
465
V
i ck = internal clock
x ck = external clock
i ck a = internal clock, asynchronous mode (asynchronous implies that TXC and RXC are two different clocks)
i ck s = internal clock, synchronous mode (synchronous implies that TXC and RXC are the same clock)
bl = bit length
wl = word length
wr = word length relative
TXC (SCKT pin) = transmit clock
RXC (SCKR pin) = receive clock
FST (FST pin) = transmit frame sync
FSR (FSR pin) = receive frame sync
HCKT (HCKT pin) = transmit high speed clock
HCKR (HCKR pin) = receive high speed clock
For the internal clock, the external clock cycle is defined by Icyc and the ESAI control register.
The word-relative frame sync signal waveform relative to the clock operates in the same manner as the bit-length frame sync
signal waveform, but spreads from one serial clock before first bit clock (same as bit length frame sync signal), until the one
before last bit clock of the first word in frame.
Periodically sampled and not 100% tested
CC
= 3.16 V ± 0.16 V; T
FST input (wl) to transmitter #0 drive enable
assertion
FST input (wl) setup time before TXC falling
edge
FST input hold time after TXC falling edge
Flag output valid after TXC rising edge
HCKR/HCKT clock cycle
HCKT input rising edge to TXC output
HCKR input rising edge to RXC output
Characteristics
Table 3-20 Enhanced Serial Audio Interface Timing (continued)
J
= 0°C to +105°C, C
1, 2, 3
DSP56364 Technical Data, Rev. 4.1
L
= 50 pF.
Symbol
Expression
Enhanced Serial Audio Interface Timing
21.0
40.0
Min
2.0
4.0
0.0
Max
31.0
32.0
18.0
27.5
27.5
Condition
x ck
x ck
x ck
i ck
i ck
i ck
4
Unit
ns
ns
ns
ns
ns
ns
ns
3-49

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