DSPB56364FU100 Freescale Semiconductor, DSPB56364FU100 Datasheet - Page 13

• Manufacturer Part Number: DSPB56364FU100
• Manufacturer: Freescale Semiconductor

Specifications of DSPB56364FU100

• Device Core Size: 24b
• Format: Fixed Point
• Clock Freq (max): 100MHz
• Mips: 100
• Device Input Clock Speed: 100MHz
• Ram Size: 9KB
• Program Memory Size: 24KB
• Operating Supply Voltage (typ): 3.3V
• Operating Supply Voltage (min): 3.14V
• Operating Supply Voltage (max): 3.46V
• Operating Temp Range: -40C to 105C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 100
• Package Type: LQFP
• Lead Free Status / Rohs Status: Not Compliant

2.8
Freescale Semiconductor
Signal
Name
HCKR
HCKT
PC2
PC5
FSR
PC1
FST
Enhanced Serial Audio Interface
Input, output, or
Input, output, or
Input, output, or
Input or output
Input or output
Input or output
Input or output
disconnected
disconnected
disconnected
Signal Type
State During
disconnected
disconnected
disconnected
disconnected
disconnected
disconnected
disconnected
Table 2-10 Enhanced Serial Audio Interface Signals
Reset
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
DSP56364 Technical Data, Rev. 4.1
High Frequency Clock for Receiver—When programmed as an input, this
signal provides a high frequency clock source for the ESAI receiver as an
alternate to the DSP core clock. When programmed as an output, this signal
can serve as a high-frequency sample clock (e.g., for external digital to analog
converters [DACs]) or as an additional system clock.
Port C 2—When the ESAI is configured as GPIO, this signal is individually
programmable as input, output, or internally disconnected.
The default state after reset is GPIO disconnected.
This input is 5 V tolerant.
High Frequency Clock for Transmitter—When programmed as an input, this
signal provides a high frequency clock source for the ESAI transmitter as an
alternate to the DSP core clock. When programmed as an output, this signal
can serve as a high frequency sample clock (e.g., for external DACs) or as an
additional system clock.
Port C 5—When the ESAI is configured as GPIO, this signal is individually
programmable as input, output, or internally disconnected.
The default state after reset is GPIO disconnected.
This input is 5 V tolerant.
Frame Sync for Receiver—This is the receiver frame sync input/output signal.
In the asynchronous mode (SYN=0), the FSR pin operates as the frame sync
input or output used by all the enabled receivers. In the synchronous mode
(SYN=1), it operates as either the serial flag 1 pin (TEBE=0), or as the
transmitter external buffer enable control (TEBE=1, RFSD=1).
When this pin is configured as serial flag pin, its direction is determined by the
RFSD bit in the RCCR register. When configured as the output flag OF1, this
pin will reflect the value of the OF1 bit in the SAICR register, and the data in the
OF1 bit will show up at the pin synchronized to the frame sync in normal mode
or the slot in network mode. When configured as the input flag IF1, the data
value at the pin will be stored in the IF1 bit in the SAISR register, synchronized
by the frame sync in normal mode or the slot in network mode.
Port C 1—When the ESAI is configured as GPIO, this signal is individually
programmable as input, output, or internally disconnected.
The default state after reset is GPIO disconnected.
This input is 5 V tolerant.
Frame Sync for Transmitter—This is the transmitter frame sync input/output
signal. For synchronous mode, this signal is the frame sync for both transmitters
and receivers. For asynchronous mode, FST is the frame sync for the
transmitters only. The direction is determined by the transmitter frame sync
direction (TFSD) bit in the ESAI transmit clock control register (TCCR).
Signal Description
Enhanced Serial Audio Interface
2-9