DSPB56364FU100 Freescale Semiconductor, DSPB56364FU100 Datasheet - Page 39

• Manufacturer Part Number: DSPB56364FU100
• Manufacturer: Freescale Semiconductor

Specifications of DSPB56364FU100

• Device Core Size: 24b
• Format: Fixed Point
• Clock Freq (max): 100MHz
• Mips: 100
• Device Input Clock Speed: 100MHz
• Ram Size: 9KB
• Program Memory Size: 24KB
• Operating Supply Voltage (typ): 3.3V
• Operating Supply Voltage (min): 3.14V
• Operating Supply Voltage (max): 3.46V
• Operating Temp Range: -40C to 105C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 100
• Package Type: LQFP
• Lead Free Status / Rohs Status: Not Compliant

Freescale Semiconductor
1
2
3
4
5
6
131
132
133
134
135
136
137
138
139
No.
152
153
154
155
156
No.
The number of wait states for Page mode access is specified in the DCR.
The refresh period is specified in the DCR.
The asynchronous delays specified in the expressions are valid for DSP56364.
All the timings are calculated for the worst case. Some of the timings are better for specific cases (e.g., tPC equals 4 ¥ TC for
read-after-read or write-after-write sequences).
BRW[1:0] (DRAM control register bits) defines the number of wait states that should be inserted in each DRAM out-of
page-access.
RD deassertion will always occur after CAS deassertion; therefore, the restricted timing is t
Page mode cycle time for two consecutive accesses of the
same direction.
Page mode cycle time for mixed (read and write) accesses.
CAS assertion to data valid (read)
Column address valid to data valid (read)
CAS deassertion to data not valid (read hold time)
Last CAS assertion to RAS deassertion
Previous CAS deassertion to RAS deassertion
CAS assertion pulse width
Last CAS deassertion to RAS assertion
CAS deassertion pulse width
Last RD assertion to RAS deassertion
RD assertion to data valid
RD deassertion to data not valid
WR assertion to data active
WR deassertion to data high impedance
• BRW[1:0] = 00
• BRW[1:0] = 01
• BRW[1:0] = 10
• BRW[1:0] = 11
Table 3-11 DRAM Page Mode Timings, Three Wait States
Table 3-12 DRAM Page Mode Timings, Four Wait States
Characteristics
Characteristics
6
DSP56364 Technical Data, Rev. 4.1
5
Symbol
Symbol
t
t
t
t
RHCP
t
t
t
t
CAC
t
RSH
CAS
CRP
t
ROH
OFF
t
t
PC
AA
CP
GA
GZ
External Memory Expansion Port (Port A)
0.75 × T
2.75 × T
3.75 × T
2.75 × T
4.25 × T
5.25 × T
7.25 × T
3.5 × T
3.5 × T
2.5 × T
Expression
2.5 × T
Expression
6 × T
2 × T
0.25 × T
1, 2, 3
1.25 × T
2 × T
C
C
C
C
C
C
C
C
C
C
C
C
C
− 4.0
− 4.0
− 4.0
OFF
C
− 4.0
− 4.0
− 7.0
1, 2, 3
(continued)
− 0.3
− 7.0
− 7.0
− 6.0
− 6.0
− 6.0
− 6.0
C
C
4
4
and not t
31.0
Min
50.0
45.0
31.0
56.0
21.0
46.5
66.5
16.0
Min
0.0
7.2
0.0
—
—
—
—
—
—
GZ
.
Max
18.0
Max
20.5
30.5
2.5
—
—
—
—
—
—
—
—
—
—
—
—
—
—
Unit
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
3-23