PEB20534H-10V2.1 Infineon Technologies, PEB20534H-10V2.1 Datasheet - Page 271

• Manufacturer Part Number: PEB20534H-10V2.1
• Description: Communication Controller 208-Pin FQFP
• Manufacturer: Infineon Technologies

PEB 20534
PEF 20534
Detailed Register Description
CHiFTDA
i = 3...0
(TX Channel 3...0)
These registers determine the last descriptor address of the channel
specific transmit descriptor chain and can be located anywhere in the 32
bit address range. The last descriptor address marks the corresponding
descriptor as the last descriptor in the transmit descriptor chain.
After write access to one of these registers, the DMA controller again
compares the first (current) transmit descriptor address (register
CHiFTDA) with the last descriptor address (register CHiLTDA), if the
corresponding DMA controller channel was in internal HOLD state.If
these addresses do not match any more, the DMA channel leaves the
internal HOLD state, re-reads the next descriptor address of the current
transmit descriptor and continues operation.
These registers are only valid, if the DMA controller is operating in Last
Descriptor Address Mode (bit CMODE set to ’1’ in register GMODE).
Note: The last descriptor addresses must be 32-bit aligned, i.e. bit 1 and
0 must be set to ’0’.
Data Sheet
271
2000-05-30