PEB20534H-10V2.1 Infineon Technologies, PEB20534H-10V2.1 Datasheet - Page 324

• Manufacturer Part Number: PEB20534H-10V2.1
• Description: Communication Controller 208-Pin FQFP
• Manufacturer: Infineon Technologies

Data Sheet
XAD1 and XAD2 bit fields are valid in HDLC modes with automatic address field
handling only (Automode, Address Mode 1, Non-Automode). They can be programmed
with one individual address byte which is inserted automatically into the address field
(8 or 16 bit) of a HDLC transmit frame. The function depends on the selected protocol
mode and address field size (bit ’ADM’ in register CCR1).
XAD2
XAD1
Transmit Address 2
2-byte address field:
Bit field XAD2 constitutes the low byte of the 2-byte address field.
(In ISDN LAP-D, the low byte is known as ’TEI’.)
1-byte address field:
According to the X.25 LAP-B protocol, XAD2 is the address of a
’RESPONSE’ frame.
Transmit Address 1
2-byte address field:
Bit field XAD1 constitutes the high byte of the 2-byte address field. Bit 1
must be set to ’0’. According to the ISDN LAP-D protocol, bit 1 is
interpreted as the C/R (COMMAND/RESPONSE) bit. This bit is
manipulated automatically by the DSCC4 according to the setting of bit
’CRI’ in register RADR:
Commands Transmit
Responses Transmit
(In ISDN LAP-D, the low byte is known as ’SAPI’.)
1-byte address field:
According to the X.25 LAP-B protocol, XAD2 is the address of a
’COMMAND’ frame.
324
bit 1
1
0
CRI=1
Detailed Register Description
(C/R)
0
1
CRI=0
PEB 20534
PEF 20534
(hdlc mode)
(hdlc mode)
2000-05-30