PEB20534H-10V2.1 Infineon Technologies, PEB20534H-10V2.1 Datasheet - Page 387

• Manufacturer Part Number: PEB20534H-10V2.1
• Description: Communication Controller 208-Pin FQFP
• Manufacturer: Infineon Technologies

11.2
11.2.1
The DSCC4 interrupt concept is based on 32-bit interrupt vectors generated by the
different blocks. Interrupt vectors are stored in a central interrupt FIFO which is 16
DWORDs deep. The interrupt controller transfers available vectors in one of ten circular
interrupt queues located in the shared memory. Each queue is dedicated to the interrupt
source.
In addition new interrupt vectors are indicated in the global status register GSTAR on a
per queue basis and selectively confirmed by writing ’1’ to the corresponding GSTAR bit
positions. The PCI interrupt signal INTA is asserted with any new interrupt event and
remains asserted until all events are confirmed.
(For more detailed information refer to chapter
Page
Data Sheet
81.)
Interrupt Queue Structure
Interrupt Queue Overview
387
“DMAC Interrupt Controller” on
Host Memory Organization
PEB 20534
PEF 20534
2000-05-30