PEB20534H-10V2.1 Infineon Technologies, PEB20534H-10V2.1 Datasheet - Page 373

• Manufacturer Part Number: PEB20534H-10V2.1
• Description: Communication Controller 208-Pin FQFP
• Manufacturer: Infineon Technologies

Data Sheet
GPIM(15:0)
GPP Interrupt Mask Control
Each bit of this bit field enables/disables interrupt generation in case of
transitions on the corresponding GPP pins. Even if not configured for
GPP operation (bit field ’PERCFG’ in register GMODE), this register
should be programmed appropriately for correct SSC or LBI operation
(masking interrupt generation).
Interrupt generation should be disabled for GPP pins, configured as
output pins via bit field ’GPDIR’ in register GPDIR.
GPIM(i)=’0’
GPIM(i)=’1’
Pin GPi interrupt generation is enabled.
Pin GPi interrupt generation is disabled.
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Detailed Register Description
PEB 20534
PEF 20534
2000-05-30
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