PEB20534H-10V2.1 Infineon Technologies, PEB20534H-10V2.1 Datasheet - Page 328

• Manufacturer Part Number: PEB20534H-10V2.1
• Description: Communication Controller 208-Pin FQFP
• Manufacturer: Infineon Technologies

Data Sheet
AMRAH2
AMRAL2
AMRAH1
AMRAL1
Receive Mask Address 2 Byte High
Receive Mask Address 2 Byte Low
Receive Mask Address 1 Byte High
Receive Mask Address 1 Byte Low
Setting a bit in this bit field to ’1’ masks the corresponding bit in bit field
{’RAH2’/’RAL2’/’RAH1’/’RAL1’} of register RADR. A masked bit position
always matches when comparing the received frame address with bit
field {’RAH2’/’RAL2’/’RAH1’/’RAL1’} allowing extended broadcast
mechanism.
bit = ’0’
bit = ’1’
The dedicated bit position is NOT masked. This bit
position in the received address must match with the
corresponding bit position in bit field {’RAH2’/’RAL2’/
’RAH1’/’RAL1’} to accept the frame.
The dedicated bit position is masked. This bit position in
the received address NEED NOT match with the
corresponding bit position in bit field {’RAH2’/’RAL2’/
’RAH1’/’RAL1’} to accept the frame.
328
Detailed Register Description
PEB 20534
PEF 20534
(hdlc mode)
(hdlc mode)
(hdlc mode)
(hdlc mode)
2000-05-30