PEB 20571 F V3.1 Infineon Technologies, PEB 20571 F V3.1 Datasheet - Page 253

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PEB 20571 F V3.1

Manufacturer Part Number
PEB 20571 F V3.1
Description
IC LINE CARD CTRLR DSP TQFP-100
Manufacturer
Infineon Technologies
Datasheet

Specifications of PEB 20571 F V3.1

Function
PBX Controller with DSP
Interface
ISDN
Voltage - Supply
3.13 V ~ 3.47 V
Current - Supply
272.6mA
Operating Temperature
0°C ~ 70°C
Mounting Type
Surface Mount
Package / Case
100-LFQFP
Includes
Layer-1 Control, Signaling Control, Signal Processing, Voice Channel Handling
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Power (watts)
-
Number Of Circuits
-
Other names
PEB20571FV3.1X
PEB20571FV31XP
SP000007539
6.2.11.5 REFCLK Control Register
REFCLK Control Register (CREFCLK) read/write
Reset value: 0003
Note: ’x’ = unused bits, read as 0.
REFCLK may be configured as an input or as an output. When configured as an input,
it may be used as a source for the on-chip DCXO 8kHz reference clock. This option is
handled by the DCXO Reference Clock Select Register (CREFSEL).
When configured as an output it is derived from XCLK input pin. In order to drive
REFCLK, XCLK may be divided by 256, 192, 4, 3 or 1.
REFCLKEN
REFDIV(2:0) REFCLK Pin Output Divider Selection
Data Sheet
15
7
x
x
REFCLK Pin Output Enable
0 =
1 =
This determines the value by which the XCLK maximum clock of 2.048
MHz is divided internally.
000 =
001 =
010 =
011 =
100 =
H
14
x
6
x
REFCLK is input, the pad is not output enabled
REFCLK is output
Division by 256
Division by 192
Division by 4
Division by 3 (default)
Division by 1
13
5
x
x
12
4
x
x
236
REFCLKEN
11
3
x
10
2
x
Register Description
REFDIV(2:0)
Address: D084
9
1
x
PEB 20570
PEB 20571
2003-07-31
8
x
0
H

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