PEB 20571 F V3.1 Infineon Technologies, PEB 20571 F V3.1 Datasheet - Page 78

• Manufacturer Part Number: PEB 20571 F V3.1
• Description: IC LINE CARD CTRLR DSP TQFP-100
• Manufacturer: Infineon Technologies

Specifications of PEB 20571 F V3.1

• Function: PBX Controller with DSP
• Interface: ISDN
• Voltage - Supply: 3.13 V ~ 3.47 V
• Current - Supply: 272.6mA
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 100-LFQFP
• Includes: Layer-1 Control, Signaling Control, Signal Processing, Voice Channel Handling
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Power (watts): -
• Number Of Circuits: -
• Other names: PEB20571FV3.1X; PEB20571FV31XP; SP000007539

LT-T Mode (Conditional States)
• F3 power down
• F3 power up
• F3 pending deactivation
• F4 pending activation
• F5/8 unsynchronized
• F6 synchronized
• F7 activated
• F7 slip detected
Data Sheet
This is the deactivated state of the physical protocol. The receive line awake unit is
active.
This state is similar to “F3 power down”. The state is invoked by a Command
TIM = “0000” (or DI static low).
The line interface reaches this state after receiving INFO 0 (from states F5 to F8).
From this state an activation is only possible from the line (transition “F3 pending
deactivation” to “F5 unsynchronized”). The power down state may be reached only
after receiving DI.
Activation has been requested from the terminal; INFO 1 is transmitted; INFO 0 is still
received; “Power Up” is transmitted in the C/I channel. This state is stable: timer T3
(ITU I.430) is to be implemented in software.
At the reception of any signal the VIP ceases to transmit INFO 1, adapts its receiver
circuit, and awaits identification of INFO 2 or INFO 4. This state is also reached after
the line interface has lost synchronism in the states F6 or F7 respectively.
When the VIP receives an activation signal (INFO 2), it responds with INFO 3 and
waits for normal frames (INFO 4).
This is the normal active state with the layer 1 protocol activated in both directions.
From state “F6 synchronized”, state F7 is reached almost 0.5 ms after reception of
INFO 4.
When a slip is detected between the T interface clocking system and the IOM-2
interface clocks (phase wander of more than 25 s, data may be disturbed) the line
interface enters this state, synchronizing again the internal buffer. After 0.5 ms this
state is relinguished.
61
Interface Description
PEB 20570
PEB 20571
2003-07-31