PEB 20571 F V3.1 Infineon Technologies, PEB 20571 F V3.1 Datasheet - Page 39

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PEB 20571 F V3.1

Manufacturer Part Number
PEB 20571 F V3.1
Description
IC LINE CARD CTRLR DSP TQFP-100
Manufacturer
Infineon Technologies
Datasheet

Specifications of PEB 20571 F V3.1

Function
PBX Controller with DSP
Interface
ISDN
Voltage - Supply
3.13 V ~ 3.47 V
Current - Supply
272.6mA
Operating Temperature
0°C ~ 70°C
Mounting Type
Surface Mount
Package / Case
100-LFQFP
Includes
Layer-1 Control, Signaling Control, Signal Processing, Voice Channel Handling
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Power (watts)
-
Number Of Circuits
-
Other names
PEB20571FV3.1X
PEB20571FV31XP
SP000007539
Table 8
Pin
No.
Used for boundary scan according to IEEE 1149.1
54
53
52
51
55
63
Data Sheet
Symbol
TMS
TDI /
SCANEN
TDO
TRST
JTCK
DSP_STOP O
JTAG and Emulation Interface Pins (DELIC-LC)
In (I)
Out (O)
I
I
I
O
I
During
Reset
I
I
I
O
I
BOOT
Strap
(pull-
down)
refer to
Table
19
After
Reset
I
I
I
O
I
O
22
Function
JTAG Test Clock
Provides the clock for JTAG test logic.
Used also for serial emulation interface.
Test Mode Select
A ’0’ to ’1’ transition on this pin is
required to step through the TAP
controller state machine.
Test Data Input
In the appropriate TAP controller state
test data or a instruction is shifted in via
this line.
Used also for serial emulation interface.
This pin must not be driven to low on the
board during reset and operation to
ensure functioning of DELIC
SCAN Enable
When both SCANMO and SCANEN are
asserted, the full-scan tests of DELIC
are activated.
Not used during normal operation.
Test Data Output
In the appropriate TAP controller state
test data or an instruction is shifted out
via this line.
Used also for serial emulation interface.
Test Reset
Provides an asynchronous reset to the
TAP controller state machine.
DSP Stop Pin
Stops external logic during breakpoints.
Activated when a stop to the DSP is
issued.
Pin Description
PEB 20570
PEB 20571
2003-07-31

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