PEF 24470 H V1.3 Infineon Technologies, PEF 24470 H V1.3 Datasheet - Page 15

• Manufacturer Part Number: PEF 24470 H V1.3
• Description: IC MTSI-XL SWITCHING MQFP100
• Manufacturer: Infineon Technologies
• Series: SWITIr

Specifications of PEF 24470 H V1.3

• Function: Switching IC
• Interface: PCM, PLL
• Number Of Circuits: 1
• Voltage - Supply: 3.13 V ~ 3.47 V
• Current - Supply: 200mA
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 100-SQFP
• Includes: Clock Shift, Data Rate Adaption, Multipoint Switching
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Power (watts): -
• Other names: PEF24470HV1.3X; SP000007617

PEF 20450 / 20470 / 24470
Overview
PRELIMINARY
1.2
Features in Detail
Flexible Data Rates
Each input and each output line of the local bus is programmable to operate at different
data rates. The possible data rates are 2.048 Mbit/s, 4.096 Mbit/s, 8.192 Mbit/s, and
16.384 Mbit/s.
Constant and Minimum Delay
Each connection independent of the addressed buses can be determined to be a
constant delay or minimum delay connection. Constant delay means that any input time-
slot or subchannel is available on the programmed output after 2 frames. Minimum delay
means that the time-slot or subchannel appears at the output as soon as possible. The
minimum delay depends on the chosen connections and the possible range is between
0 and 2 frames.
Subchannel Switching
Each connection can be a 1-bit, 2-bit, 4-bit, or 8-bit connection. Subchannel switching
has a constant delay of 2 frames. Subchannel switching is supported only for data rate
of 2.048 Mbit/s, 4.096 Mbit/s and 8.192 Mbit/s.
Programmable Clock Shift
The position of time-slot 0 of each local bus input line can be programmed within the
time-slot before and after the PFS rising edge in half bit steps. Also the position of time-
slot 0 of all local bus output lines can be programmed within the first time-slot after the
PFS rising edge.
Automatic Data Rate Adaption
Connections are also possible between lines operating at different data rates. The
programmer just specifies input and output line, time-slot, and if necessary, the
subchannel.
Parallel Mode
The first 8 local bus input and output lines can be configured to one parallel input or
output port respectively. In serial mode a time-slot is determined by 8 consecutive data
clock cycles according to each line. In parallel mode a time-slot is determined by 1 data
clock cycle according to the first 8 lines.
Preliminary Data Sheet
6
2001-11-20