PEF 24470 H V1.3 Infineon Technologies, PEF 24470 H V1.3 Datasheet - Page 43

• Manufacturer Part Number: PEF 24470 H V1.3
• Description: IC MTSI-XL SWITCHING MQFP100
• Manufacturer: Infineon Technologies
• Series: SWITIr

Specifications of PEF 24470 H V1.3

• Function: Switching IC
• Interface: PCM, PLL
• Number Of Circuits: 1
• Voltage - Supply: 3.13 V ~ 3.47 V
• Current - Supply: 200mA
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 100-SQFP
• Includes: Clock Shift, Data Rate Adaption, Multipoint Switching
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Power (watts): -
• Other names: PEF24470HV1.3X; SP000007617

PRELIMINARY
4.5.1
Via 8 output lines it is possible to provide 8 different framing signals which are used for
synchronization purpose. All signals have a period of 125 µs. Their offset can be
programmed individually within the PFS determined frame in a resolution of 61 ns (i.e.
1/16.384 MHz). The default start point for the offset is the beginning of a frame (rising
edge of PFS and the clock signal). The start point for the offset can be shifted for an half
clock cycle, that means the second start point is determined with the rising edge of PFS
and the next falling edge of the clock signal (as shown in
the signal can also be programmed in steps of 61 ns. All frame signals can be controlled
as high or low active.
Figure 14
Figure 14
clock cycle with a length of 4 clock cycles. Further programming examples can be found
in
4.5.2
All 8 GPCLK lines can be configured as individual clock outputs with 8 kHz, 2.048 MHz,
4.096 MHz, 8.192 MHz, 16.384 MHz and for test purposes with the internal frequency or
the input frequency of the analog PLL (APLL). All clock signals are generated from the
analog PLL output frequency which is the internal frequency. The quality of all output
frequency signals depends on the quality of the selected input PLL frequency.
Preliminary Data Sheet
Chapter
16.384 Mbit/s
Frame Signal
PFS
shows an example of a frame signal beginning with the rising edge of the 64th
Frame Group Outputs
GPCLK as Clock Outputs
6.8.1.
0
Frame Signal Example
1
125µs
64
34
PEF 20450 / 20470 / 24470
Figure
125µs
Description of Interfaces
14). The high time of
2001-11-20
switi_038.emf