PEF 24470 H V1.3 Infineon Technologies, PEF 24470 H V1.3 Datasheet - Page 22

• Manufacturer Part Number: PEF 24470 H V1.3
• Description: IC MTSI-XL SWITCHING MQFP100
• Manufacturer: Infineon Technologies
• Series: SWITIr

Specifications of PEF 24470 H V1.3

• Function: Switching IC
• Interface: PCM, PLL
• Number Of Circuits: 1
• Voltage - Supply: 3.13 V ~ 3.47 V
• Current - Supply: 200mA
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 100-SQFP
• Includes: Clock Shift, Data Rate Adaption, Multipoint Switching
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Power (watts): -
• Other names: PEF24470HV1.3X; SP000007617

PRELIMINARY
Table 5
Pin No.
67
66
1)
2.2.4
Table 6
Pin No.
51
52
55
53
54
2.2.5
Table 7
Pin No.
60
3
Preliminary Data Sheet
73 is GPCLK7, 74 is GPCLK6, 75 is GPCLK5..
Symbol
CS
RD
DS
Symbol
NTWK_1
NTWK_2
Symbol
TCK
TMS
TRST
TDO
TDI
JTAG Interface
Microprocessor Interface
Clock Pins (cont’d)
JTAG Interface
Microprocessor Interface
Out (O)
Out (O)
Out (O)
In (I)
In (I)
In (I)
O
I
I
I
I
I
I
I
I
Function
Chip Select
Active low. A "low" on this line selects all registers for read/
write operations.
Read (Intel/Infineon Mode)
Indicates a read access.
Data Strobe (Motorola Mode)
During a read cycle, DS indicates that the device should
place valid data on the bus. During a write access, DS
indicates that valid data is on the bus.
Function
Test Clock
Single rate test data clock.
Test Mode Select
A ’0’ to ’1’ transition on this pin is required to step through
the TAP controller state machine.
Test Reset
Resets the TAP controller state machine (asynchronous
reset).
Test Data Out
In the appropriate TAP controller state test data or a
instruction is shifted out via this line.
Test Data Input
In the appropriate TAP controller state test data or a
instruction is shifted in via this line.
Function
Primary Network Timing Reference Input
Optionally the PLL can be synchronized to this input which
can be 8 kHz, 512 kHz, 1.536 MHz, 1.544 MHz, 2.048 MHz
Secondary Network Timing Reference Input
Optionally the PLL can be synchronized to this input which
can be 8 kHz, 512 kHz, 1.536 MHz, 1.544 MHz, 2.048 MHz
13
PEF 20450 / 20470 / 24470
Pin Description
Reset
Behavior
Reset
Behavior
Reset
Behavior
High Z
2001-11-20