SC28L201A1DGG,118 NXP Semiconductors, SC28L201A1DGG,118 Datasheet - Page 13

• Manufacturer Part Number: SC28L201A1DGG,118
• Description: IC UART W/FIFO 48-TSSOP
• Manufacturer: NXP Semiconductors
• Series: IMPACTr

Specifications of SC28L201A1DGG,118

• Features: False-start Bit Detection
• Number Of Channels: 2, DUART
• Fifo's: 256 Byte
• Voltage - Supply: 3.3V, 5V
• With Parallel Port: Yes
• With Auto Flow Control: Yes
• With False Start Bit Detection: Yes
• With Modem Control: Yes
• With Cmos: Yes
• Mounting Type: Surface Mount
• Package / Case: 48-TSSOP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 935277824118; SC28L201A1DGG-T; SC28L201A1DGG-T

Philips Semiconductors
7. Detailed descriptions
9397 750 13138
Product data sheet
7.1.1 DACKN cycle (68000 mode)
7.1 Bus interface
Remark: For the convenience of the reader, some paragraphs of the following sections
are repeated in descriptions of closely linked functions described in other sections.
The bus interface operates in two modes selected by the MODE_IM pin. If this pin is HIGH
or left open, the I or 80xxx mode, the signal DACKN signal is not generated or used, and
data flow to and from the chip is controlled by the state of the CEN, RDN, WRN pin
combination. If the MODE_IM pin is tied LOW, the M or 68000 mode, the data is written to
the device when the DACKN pin is asserted LOW by the UART. Read data is presented by
a delay from CEN active.
The Host interface in the 80xxx mode is comprised of the signal pins CEN, WRN, RDN.
The data is written to the chip on the rise of CEN or WRN, whichever one occurs first.
Data is presented to the bus on the condition of both CEN and RDN being LOW. In the
read condition, the data bus is returned to high-impedance on the rise of CEN or RDN,
whichever one returns HIGH first.
When in the M or 68000 mode, several control pins change function to provide the signals
CEN, R/WN, IACKN, DACKN. When CEN is LOW and R/WN is LOW, data will be written
to the chip when the DACKN occurs. In a read condition, data will be presented to the bus
when CEN is LOW and R/WN is HIGH. DACKN will signal when the data on the bus is
valid. The data bus will return to high-impedance with CEN returns HIGH.
The assertion if IACKN (in either mode) will cause the interrupt vector or the interrupt
vector modified by the context of the interrupt source to be placed on the bus. In the
68000 mode, the assertion of IACKN will also generate a DACKN cycle. Addressing of the
various functions of the UART is through the address bus A[6:0]. Data is presented on the
8-bit data bus.
When operating in the 68000 mode, bus cycle completion is indicated by the DACKN pin
(an open-drain signal) going LOW. The timing of DACKN is controlled by GCCR[7:6]
where three time delays area available. The delay begins with the falling edge of CEN.
DACKN is presented after
edges of the X1/SCLK and will be realized when the bus cycle begins just before the
transition of X1/SCLK. Usually in this mode the address and data are set up with respect
to the leading edge of the bus cycle. Timing diagrams for this mode are drawn with
DACKN in consideration. When CEN is withdrawn before DACKN occurs, the generation
of the DACKN signal and bus cycle will be terminated. In this case, the bus timing will
return to that of Intel-type timing for that particular cycle. This timing should not be less
than the minimum read or write pulse.
The DACKN pin is an open-drain driver. At the termination of an access to the SC28L201
DACKN drives the pin to high-impedance until the next DACKN cycle. This will occur at
the termination of the CEN or IACKN cycle.
Remark: The faster 86xxx timing may be used in the 68000 mode if the bus cycles are
faster than
generation of DACKN. In this case, bus timing is effectively that of the 86xxx mode.
1
2
period of the SCLK clock. Withdrawing CEN before DACKN prevents the
Rev. 01 — 31 October 2005
1
2
to three periods of X1/SCLK. The minimum time will be two
3.3 V, 5 V UART, 3.125 Mbit/s, with 256-byte FIFO
© Koninklijke Philips Electronics N.V. 2005. All rights reserved.
SC28L201
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