SC28L201A1DGG,118 NXP Semiconductors, SC28L201A1DGG,118 Datasheet - Page 87

• Manufacturer Part Number: SC28L201A1DGG,118
• Description: IC UART W/FIFO 48-TSSOP
• Manufacturer: NXP Semiconductors
• Series: IMPACTr

Specifications of SC28L201A1DGG,118

• Features: False-start Bit Detection
• Number Of Channels: 2, DUART
• Fifo's: 256 Byte
• Voltage - Supply: 3.3V, 5V
• With Parallel Port: Yes
• With Auto Flow Control: Yes
• With False Start Bit Detection: Yes
• With Modem Control: Yes
• With Cmos: Yes
• Mounting Type: Surface Mount
• Package / Case: 48-TSSOP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 935277824118; SC28L201A1DGG-T; SC28L201A1DGG-T

Philips Semiconductors
Table 78:
The register map for channel A (UART A).
9397 750 13138
Product data sheet
A[6:0]
010 0000 (0x20)
010 0001 (0x21)
010 0010 (0x22)
010 0011 (0x23)
010 0100 (0x24)
010 0101 (0x25)
010 0110 (0x26)
010 0111 (0x27)
010 1000 (0x28)
010 1001 (0x29)
010 1010 (0x2A)
010 1011 (0x2B)
010 1100 (0x2C) Counter/Timer Clock Source (CTCS 1)
010 1101 (0x2D)
010 1110 (0x2E)
010 1111 (0x2F)
011 0000 (0x30)
011 0001 (0x31)
011 0010 (0x32)
011 0011 (0x33)
011 0100 (0x34)
011 0101 (0x35)
011 0110 (0x36)
011 0111 (0x37)
011 1000 (0x38)
011 1001 (0x39)
011 1010 (0x3A) Input Port Change Interrupt Enable (IPCE B)
011 1011 (0x3B)
011 1100 (0x3C)
011 1101 (0x3D)
011 1110 (0x3E)
011 1111 (0x3F)
Register map summary
Read
Mode Register 0 (MR0 A)
Mode Register 1 (MR1 A)
Mode Register 2 (MR2 A)
Mode Register 3 (MR3 A)
Counter/Timer Clock Source (CTCS 0)
Interrupt Status Register (ISR A)
Programmable BRG Preset Lower (PBRGPL 0)
Programmable BRG Preset Upper (PBRGPU 0)
Receiver Clock Select Register (RxCSR A)
Transmitter Clock Select Register (TxCSR A)
Input Port Change Interrupt Enable (IPCE A)
Programmable BRG Clock Source (PBRGCS)
Programmable BRG Preset Lower (PBRGPL 1)
Programmable BRG Preset Upper (PBRGPU 1)
Rev. 01 — 31 October 2005
3.3 V, 5 V UART, 3.125 Mbit/s, with 256-byte FIFO
Write
Mode Register 0 (MR0 A)
Mode Register 1 (MR1 A)
Mode Register 2 (MR2 A)
Mode Register 3 (MR3 A)
Counter/Timer Clock Source (CTCS 0)
Interrupt Mask Register (IMR A)
Programmable BRG Preset Lower (PBRGPL 0)
Programmable BRG Preset Upper (PBRGPU 0)
Counter/Timer Clock Source (CTCS 1)
Receiver Clock Select Register (RxCSR A)
Transmitter Clock Select Register (TxCSR A)
Input Port Change Interrupt Enable (IPCE A)
Programmable BRG Clock Source (PBRGCS)
Programmable BRG Preset Lower (PBRGPL 1)
Programmable BRG Preset Upper (PBRGPU 1)
Input Port Change Interrupt Enable (IPCE B)
© Koninklijke Philips Electronics N.V. 2005. All rights reserved.
SC28L201
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