SC28L201A1DGG,118 NXP Semiconductors, SC28L201A1DGG,118 Datasheet - Page 8

• Manufacturer Part Number: SC28L201A1DGG,118
• Description: IC UART W/FIFO 48-TSSOP
• Manufacturer: NXP Semiconductors
• Series: IMPACTr

Specifications of SC28L201A1DGG,118

• Features: False-start Bit Detection
• Number Of Channels: 2, DUART
• Fifo's: 256 Byte
• Voltage - Supply: 3.3V, 5V
• With Parallel Port: Yes
• With Auto Flow Control: Yes
• With False Start Bit Detection: Yes
• With Modem Control: Yes
• With Cmos: Yes
• Mounting Type: Surface Mount
• Package / Case: 48-TSSOP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 935277824118; SC28L201A1DGG-T; SC28L201A1DGG-T

Philips Semiconductors
Table 3:
See
9397 750 13138
Product data sheet
Symbol
MODE_IM
D0 to D7
CEN
R/WN
IACKN
DACKN
A6 to A0
RESETN
IRQN
X1/SCLK
X2
RXD
TXD
I/O7A to I/O0A
Figure
4.
Pin description for 68000 bus interface (Motorola)
Pin
19
18, 17, 16,
15, 12, 11,
10, 9
26
27
23
28
3, 4, 5, 6,
20, 21, 22
8
46
47
48
7
45
37, 38, 39,
40, 41, 42,
43, 44
Type
I
I/O
I
I
I
O
I
I
O
I
O
I
O
I/O
Description
Bus configuration. When LOW, configures the bus interface to the conditions
shown in this table.
Data bus. Bidirectional 3-state data bus used to transfer commands, data and status
between the UART and the CPU. D0 is the least significant bit.
Chip Enable. Active LOW input signal. When LOW, data transfers between the CPU
and the UART are enabled on D[0:7] as controlled by the R/WN and A6 to A0 inputs.
When HIGH, places the D[0:7] lines in the 3-state condition.
Read/Write. Input signal. When CEN is LOW, R/WN HIGH inputs a read cycle, when
LOW a write cycle.
Interrupt acknowledge. Active LOW input indicates an interrupt acknowledge
cycle. Usually asserted by the CPU in response to an interrupt request. When
asserted, places the interrupt vector on the bus and asserts DACKN.
Data transfer acknowledge. An open-drain active LOW output asserted in a write,
read, or interrupt acknowledge cycle to indicate proper transfer of data between the
CPU and the UART.
Address inputs. Select the UART internal registers and ports for read/write
operations.
Reset. A LOW level clears internal registers (SR, IMR, ISR, OPR, OPCR), places
I/O[7:0] A and B at high-impedance input state, stops the counter/timer, and puts
Channel in the inactive state, with the TXD output in the ‘mark’ (HIGH) state. Sets
MR pointer to MR1 9600 baud, 1 start, no parity and 1 stop bit(s).
Interrupt request. Active LOW, open-drain output which signals the CPU that one
or more of the eleven (11) maskable interrupting conditions are true.
Crystal 1. Crystal or external clock input. A crystal or clock of the specified limits
must be supplied at all times. When a crystal is used, a capacitor must be connected
from this pin to ground (see
Crystal 2. Connection for other side of the crystal. When a crystal is used, a
capacitor must be connected from this pin to ground (see Figure 12). If X1/SCLK is
driven from an external source, this pin must be open or not driving more than
2 CMOS or TTL loads.
Channel Receiver serial data input. The least significant bit is received first. ‘Mark’
is HIGH; ‘space’ is LOW.
Channel Transmitter serial data output. The least significant bit is transmitted first.
This output is held in the ‘mark’ condition when the transmitter is disabled, idle or
when operating in local loopback mode. ‘Mark’ is HIGH; ‘space’ is LOW.
General-purpose input and output ports. The character of these pins is controlled
by I/OPCR. They may be inputs or outputs and will present many internal clocks and
interrupt signals: RTS, CTS, DTR, DSR, and so on. All have change-of-state
detectors and the input is always active. These pins are set to input only when
addressed from the low order 16 address space. When these pins are configured for
interrupt type signals (RXRDY, TXRDY, C/TRDY), they switch to open-drain outputs.
Each of these pins has a small pull-up ‘resistor’ that supplies approximately 5 A of
current.
Rev. 01 — 31 October 2005
3.3 V, 5 V UART, 3.125 Mbit/s, with 256-byte FIFO
Figure
14).
© Koninklijke Philips Electronics N.V. 2005. All rights reserved.
SC28L201
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