AT90PWM3B Atmel Corporation, AT90PWM3B Datasheet - Page 247
AT90PWM3B
Manufacturer Part Number
AT90PWM3B
Description
Manufacturer
Atmel Corporation
Specifications of AT90PWM3B
Flash (kbytes)
8 Kbytes
Pin Count
32
Max. Operating Frequency
16 MHz
Cpu
8-bit AVR
# Of Touch Channels
8
Hardware Qtouch Acquisition
No
Max I/o Pins
27
Ext Interrupts
4
Usb Speed
No
Usb Interface
No
Spi
1
Uart
1
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
11
Adc Resolution (bits)
10
Adc Speed (ksps)
125
Analog Comparators
3
Resistive Touch Screen
No
Dac Channels
1
Dac Resolution (bits)
10
Temp. Sensor
No
Crypto Engine
No
Sram (kbytes)
0.5
Eeprom (bytes)
512
Self Program Memory
YES
Dram Memory
No
Nand Interface
No
Picopower
No
Temp. Range (deg C)
-40 to 105
I/o Supply Class
2.7 to 5.5
Operating Voltage (vcc)
2.7 to 5.5
Fpu
No
Mpu / Mmu
no / no
Timers
5
Output Compare Channels
16
Input Capture Channels
1
Pwm Channels
12
32khz Rtc
No
Calibrated Rc Oscillator
Yes
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21.8.2
4317J–AVR–08/10
ADC Control and Status Register A – ADCSRA
• Bit 3, 2, 1, 0 – MUX3, MUX2, MUX1, MUX0: ADC Channel Selection Bits
These 4 bits determine which analog inputs are connected to the ADC input. The different set-
ting are shown in
Table 21-4.
If these bits are changed during a conversion, the change will not take effect until this conversion
is complete (it means while the ADIF bit in ADCSRA register is set).
Bit
Read/Write
Initial Value
• Bit 7 – ADEN: ADC Enable Bit
Set this bit to enable the ADC.
Clear this bit to disable the ADC.
Clearing this bit while a conversion is running will take effect at the end of the conversion.
• Bit 6– ADSC: ADC Start Conversion Bit
Set this bit to start a conversion in single conversion mode or to start the first conversion in free
running mode.
Cleared by hardware when the conversion is complete. Writing this bit to zero has no effect.
The first conversion performs the initialization of the ADC.
• Bit 5 – ADATE: ADC Auto trigger Enable Bit
Set this bit to enable the auto triggering mode of the ADC.
Clear it to return in single conversion mode.
MUX3
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
ADC Input Channel Selection
MUX2
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
ADEN
R/W
7
0
Table
21-4.
ADSC
R/W
6
0
MUX1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
ADATE
R/W
5
0
ADIF
R
MUX0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
4
0
ADIE
R/W
3
0
AT90PWM2/3/2B/3B
Description
ADC0
ADC1
ADC2
ADC3
ADC4
ADC5
ADC6
ADC7
ADC8
ADC9
ADC10
AMP0
AMP1 (- is ADC8, + is ADC9)
Reserved
Bandgap
GND
ADPS2
R/W
2
0
ADPS1
R/W
1
0
ADPS0
R/W
0
0
ADCSRA
247
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