AT90PWM3B Atmel Corporation, AT90PWM3B Datasheet - Page 259

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AT90PWM3B

Manufacturer Part Number
AT90PWM3B
Description
Manufacturer
Atmel Corporation
Datasheets

Specifications of AT90PWM3B

Flash (kbytes)
8 Kbytes
Pin Count
32
Max. Operating Frequency
16 MHz
Cpu
8-bit AVR
# Of Touch Channels
8
Hardware Qtouch Acquisition
No
Max I/o Pins
27
Ext Interrupts
4
Usb Speed
No
Usb Interface
No
Spi
1
Uart
1
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
11
Adc Resolution (bits)
10
Adc Speed (ksps)
125
Analog Comparators
3
Resistive Touch Screen
No
Dac Channels
1
Dac Resolution (bits)
10
Temp. Sensor
No
Crypto Engine
No
Sram (kbytes)
0.5
Eeprom (bytes)
512
Self Program Memory
YES
Dram Memory
No
Nand Interface
No
Picopower
No
Temp. Range (deg C)
-40 to 105
I/o Supply Class
2.7 to 5.5
Operating Voltage (vcc)
2.7 to 5.5
Fpu
No
Mpu / Mmu
no / no
Timers
5
Output Compare Channels
16
Input Capture Channels
1
Pwm Channels
12
32khz Rtc
No
Calibrated Rc Oscillator
Yes

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22.2
22.3
4317J–AVR–08/10
Operation
Starting a Conversion
Figure 22-1. Digital to Analog Converter Block Schematic
The Digital to Analog Converter generates an analog signal proportional to the value of the DAC
registers value.
In order to have an accurate sampling frequency control, there is the possibility to update the
DAC input values through different trigger events.
The DAC is configured thanks to the DACON register. As soon as the DAEN bit in DACON reg-
ister is set, the DAC converts the value present on the DACH and DACL registers in accordance
with the register DACON setting.
Alternatively, a conversion can be triggered automatically by various sources. Auto Triggering is
enabled by setting the DAC Auto Trigger Enable bit, DAATE in DACON. The trigger source is
selected by setting the DAC Trigger Select bits, DATS in DACON (See description of the DATS
bits for a list of the trigger sources). When a positive edge occurs on the selected trigger signal,
the DAC converts the value present on the DACH and DACL registers in accordance with the
register DACON setting. This provides a method of starting conversions at fixed intervals. If the
trigger signal is still set when the conversion completes, a new conversion will not be started. If
another positive edge occurs on the trigger signal during conversion, the edge will be ignored.
Note that an interrupt flag will be set even if the specific interrupt is disabled or the Global Inter-
Detector
Edge
DAATE
DAC High bits
VRef
DACH
DATS2
10
DATS1
Update DAC
Trigger
1
DAC
10
0
DATS0
10
DACON
DACL
DAC Low bits
-
Result
AT90PWM2/3/2B/3B
DAC
DALA
Output
Driver
DAOE
DAEN
D2A pin
259

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