AT90PWM81 Atmel Corporation, AT90PWM81 Datasheet - Page 133
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AT90PWM81
Manufacturer Part Number
AT90PWM81
Description
Manufacturer
Atmel Corporation
Datasheet
1.AT90PWM161.pdf
(325 pages)
Specifications of AT90PWM81
Flash (kbytes)
8 Kbytes
Pin Count
20
Max. Operating Frequency
16 MHz
Cpu
8-bit AVR
Hardware Qtouch Acquisition
No
Max I/o Pins
20
Ext Interrupts
3
Usb Speed
No
Usb Interface
No
Spi
1
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
11
Adc Resolution (bits)
10
Adc Speed (ksps)
125
Analog Comparators
3
Resistive Touch Screen
No
Dac Channels
1
Dac Resolution (bits)
10
Temp. Sensor
Yes
Crypto Engine
No
Sram (kbytes)
0.25
Eeprom (bytes)
512
Self Program Memory
YES
Dram Memory
No
Nand Interface
No
Picopower
No
Temp. Range (deg C)
-40 to 125
I/o Supply Class
2.7 to 5.5
Operating Voltage (vcc)
2.7 to 5.5
Fpu
No
Mpu / Mmu
no / no
Timers
1
Output Compare Channels
8
Input Capture Channels
1
Pwm Channels
6
32khz Rtc
No
Calibrated Rc Oscillator
Yes
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12.24.1
12.25 PSC Register Definition
12.25.1
7734P–AVR–08/10
List of Interrupt Vector
PSC 2 Synchro and Output Configuration – PSOC2
Each PSC provides 3 interrupt vectors
See “PSC2 Interrupt Mask Register – PIM2” on page 143.
.
Registers are explained for PSC0. They are identical for PSC1. For PSC2 only different registers are
described.
Bit
Read/Write
Initial Value
• Bit 7 – POS23 : PSCOUT23 Selection (PSC2 only)
When this bit is clear, PSCOUT23 outputs the waveform generated by Waveform Generator B.
When this bit is set, PSCOUT23 outputs the waveform generated by Waveform Generator A.
• Bit 6 – POS22 : PSCOUT22 Selection (PSC2 only)
When this bit is clear, PSCOUT22 outputs the waveform generated by Waveform Generator A.
When this bit is set, PSCOUT22 outputs the waveform generated by Waveform Generator B.
• Bit 5:4 – PSYNCn1:0: Synchronization Out for ADC Selection
Select the polarity and signal source for generating a signal which will be sent to the ADC for
synchronization.
Table 12-11.
PSYNCn1
0
0
1
1
• PSCn EC (End of Cycle): When enabled and when a match with OCRnRB occurs
• PSCn EEC (End of Enhanced Cycle): When enabled and when a match with OCRnRB occurs at the
• PSCn CAPT (Capture Event): When enabled and one of the two following events occurs : retrigger,
15th enhanced cycle
capture of the PSC counter or Synchro Error.
R/W
7
POS23
0
Synchronization Source Description in One/Two/Four Ramp Modes
PSYNCn0
0
1
0
1
6
POS22
R/W
0
Description
Send signal on leading edge of PSCOUTn0 (match with OCRnSA)
Send signal on trailing edge of PSCOUTn0 (match with OCRnRA or
fault/retrigger on part A)
Send signal on leading edge of PSCOUTn1 (match with OCRnSB)
Send signal on trailing edge of PSCOUTn1 (match with OCRnRB or
fault/retrigger on part B)
5
PSYNC21
R/W
0
4
PSYNC20
R/W
0
3
POEN2D
R/W
0
2
POEN2B
R/W
0
1
POEN2C
R/W
0
AT90PWM81
0
POEN2A
R/W
0
PSOC2
133
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