AT90PWM81 Atmel Corporation, AT90PWM81 Datasheet - Page 218
AT90PWM81
Manufacturer Part Number
AT90PWM81
Description
Manufacturer
Atmel Corporation
Datasheet
1.AT90PWM161.pdf
(325 pages)
Specifications of AT90PWM81
Flash (kbytes)
8 Kbytes
Pin Count
20
Max. Operating Frequency
16 MHz
Cpu
8-bit AVR
Hardware Qtouch Acquisition
No
Max I/o Pins
20
Ext Interrupts
3
Usb Speed
No
Usb Interface
No
Spi
1
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
11
Adc Resolution (bits)
10
Adc Speed (ksps)
125
Analog Comparators
3
Resistive Touch Screen
No
Dac Channels
1
Dac Resolution (bits)
10
Temp. Sensor
Yes
Crypto Engine
No
Sram (kbytes)
0.25
Eeprom (bytes)
512
Self Program Memory
YES
Dram Memory
No
Nand Interface
No
Picopower
No
Temp. Range (deg C)
-40 to 125
I/o Supply Class
2.7 to 5.5
Operating Voltage (vcc)
2.7 to 5.5
Fpu
No
Mpu / Mmu
no / no
Timers
1
Output Compare Channels
8
Input Capture Channels
1
Pwm Channels
6
32khz Rtc
No
Calibrated Rc Oscillator
Yes
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17.8.2
218
AT90PWM81
ADC Control and Status Register A – ADCSRA
Table 17-4.
If these bits are changed during a conversion, the change will not take effect until this conversion is com-
plete (it means while the ADIF bit in ADCSRA register is set).
Bit
Read/Write
Initial Value
• Bit 7 – ADEN: ADC Enable Bit
Set this bit to enable the ADC.
Clear this bit to disable the ADC.
Clearing this bit while a conversion is running will take effect at the end of the conversion.
• Bit 6– ADSC: ADC Start Conversion Bit
Set this bit to start a conversion in single conversion mode or to start the first conversion in free running
mode.
Cleared by hardware when the conversion is complete. Writing this bit to zero has no effect.
The first conversion performs the initialization of the ADC.
• Bit 5 – ADATE: ADC Auto trigger Enable Bit
Set this bit to enable the auto triggering mode of the ADC.
Clear it to return in single conversion mode.
In auto trigger mode the trigger source is selected by the ADTS bits in the ADCSRB register. See
17-6 on page
• Bit 4– ADIF: ADC Interrupt Flag
Set by hardware as soon as a conversion is complete and the Data register are updated with the conversion
result.
Cleared by hardware when executing the corresponding interrupt handling vector.
Alternatively, ADIF can be cleared by writing it to logical one.
• Bit 3– ADIE: ADC Interrupt Enable Bit
Set this bit to activate the ADC end of conversion interrupt.
Clear it to disable the ADC end of conversion interrupt.
• Bit 2, 1, 0– ADPS2, ADPS1, ADPS0: ADC Prescaler Selection Bits
These 3 bits determine the division factor between the system clock frequency and input clock of the
ADC.
The different setting are shown in
MUX3
1
1
1
220.
7
ADEN
R/W
0
ADC Input Channel Selection
MUX2
1
1
1
6
ADSC
R/W
0
MUX1
0
1
1
Table 17-5 on page
R/W
5
ADATE
0
4
ADIF
R
0
MUX0
1
0
1
219.
3
ADIE
R/W
0
2
ADPS2
R/W
0
Description
VCC/4
Bandgap (Vbg)
GND
R/W
1
ADPS1
0
0
ADPS0
R/W
0
7734P–AVR–08/10
ADCSRA
Table
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