AT90PWM81 Atmel Corporation, AT90PWM81 Datasheet - Page 21

• Manufacturer Part Number: AT90PWM81
• Manufacturer: Atmel Corporation

Specifications of AT90PWM81

• Flash (kbytes): 8 Kbytes
• Pin Count: 20
• Max. Operating Frequency: 16 MHz
• Cpu: 8-bit AVR
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 20
• Ext Interrupts: 3
• Usb Speed: No
• Usb Interface: No
• Spi: 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 11
• Adc Resolution (bits): 10
• Adc Speed (ksps): 125
• Analog Comparators: 3
• Resistive Touch Screen: No
• Dac Channels: 1
• Dac Resolution (bits): 10
• Temp. Sensor: Yes
• Crypto Engine: No
• Sram (kbytes): 0.25
• Eeprom (bytes): 512
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: No
• Picopower: No
• Temp. Range (deg C): -40 to 125
• I/o Supply Class: 2.7 to 5.5
• Operating Voltage (vcc): 2.7 to 5.5
• Fpu: No
• Mpu / Mmu: no / no
• Timers: 1
• Output Compare Channels: 8
• Input Capture Channels: 1
• Pwm Channels: 6
• 32khz Rtc: No
• Calibrated Rc Oscillator: Yes

4.3.5
7734P–AVR–08/10
Program multiple bytes in one Atomic operation
Caution: An interrupt between step 5 and step 6 will make the write cycle fail, since the EEPROM Master
Write Enable will time-out. If an interrupt routine accessing the EEPROM is interrupting another
EEPROM access, the EEAR or EEDR Register will be modified, causing the interrupted EEPROM access
to fail. It is recommended to have the Global Interrupt Flag cleared during all the steps to avoid these
problems.
When the write access time has elapsed, the EEWE bit is cleared by hardware. The user software can poll
this bit and wait for a zero before writing the next byte. When EEWE has been set, the CPU is halted for
two cycles before the next instruction is executed.
• Bit 0 – EERE: EEPROM Read Enable
The EEPROM Read Enable Signal EERE is the read strobe to the EEPROM. When the correct address is
set up in the EEAR Register, the EERE bit must be written to a logic one to trigger the EEPROM read.
The EEPROM read access takes one instruction, and the requested data is available immediately. When
the EEPROM is read, the CPU is halted for four cycles before the next instruction is executed.
The user should poll the EEWE bit before starting the read operation. If a write operation is in progress, it
is neither possible to read the EEPROM, nor to change the EEAR Register.
The calibrated Oscillator is used to time the EEPROM accesses.
time for EEPROM access from the CPU.
Table 4-2.
It is possible to write multiple bytes into the EEPROM. Before initiating a programming (erase/write), the
data to be written has to be loaded into the temporary EEPROM page buffer. Writing EEPAGE to one
enables a load operation.
When EEPAGE bit is written to one, the temporary EEPROM page buffer is ready for loading. To load
data into the temporary EEPROM page buffer, the address and data must be written into EEARL and
EEDR respectively. Note that the data is loaded when EEDR is updated. Therefore, the address must be
written before data. This operation is repeated until the temporary EEPROM page buffer is filled up or
until all data to be written have been loaded. The number of bytes that is loaded must not exceed the tem-
porary EEPROM page size before performing a program operation. Note that it is not possible to write
more than one time to each byte in the temporary EEPROM page buffer before executing a program oper-
ation. If the same byte is written multiple times, the content in the temporary EEPROM page will be bit
wise AND between the written data (i.e. if 0xaa and 0x55 is loaded to the same byte, the result will be
0x00). The temporary EEPROM buffer will be ready for new data after the program operation has com-
pleted. Alternatively, the temporary EEPROM buffer is flushed and ready for new data by writing EEPE
(within four cycles after EEMPE is written) if the EEPMn bits are 0b11. When the temporary EEPROM
buffer is flushed, the EEPAGE bit will be cleared. Loading data into the temporary EEPROM buffer takes
three CPU clock cycles. If EEDR is written while EEPAGE is set, the CPU is halted to ensure that the
operation takes three cycles.
Symbol
EEPROM write
(from CPU)
EEPROM Programming Time.
Number of Calibrated RC Oscillator Cycles
26368
Table 4-2
lists the typical programming
Typ Programming Time
AT90PWM81
3.3 ms
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