ATmega32U2 Atmel Corporation, ATmega32U2 Datasheet - Page 177
ATmega32U2
Manufacturer Part Number
ATmega32U2
Description
Manufacturer
Atmel Corporation
Specifications of ATmega32U2
Flash (kbytes)
32 Kbytes
Pin Count
32
Max. Operating Frequency
16 MHz
Cpu
8-bit AVR
# Of Touch Channels
12
Hardware Qtouch Acquisition
No
Max I/o Pins
22
Ext Interrupts
20
Usb Transceiver
1
Usb Speed
Full Speed
Usb Interface
Device
Spi
2
Uart
1
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Analog Comparators
1
Resistive Touch Screen
No
Temp. Sensor
No
Crypto Engine
No
Sram (kbytes)
1
Eeprom (bytes)
1024
Self Program Memory
YES
Dram Memory
No
Nand Interface
No
Picopower
No
Temp. Range (deg C)
-40 to 85
I/o Supply Class
2.7 to 5.5
Operating Voltage (vcc)
2.7 to 5.5
Fpu
No
Mpu / Mmu
no / no
Timers
2
Output Compare Channels
5
Input Capture Channels
1
Pwm Channels
4
32khz Rtc
No
Calibrated Rc Oscillator
Yes
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Table 19-1.
19.4
Table 19-2.
7799D–AVR–11/10
Operating Mode
Synchronous Master mode
UCPOLn
SPI Data Modes and Timing
0
0
1
1
Equations for Calculating Baud Rate Register Setting
UCPOLn and UCPHAn Functionality-
UCPHAn
Note:
There are four combinations of XCKn (SCK) phase and polarity with respect to serial data, which
are determined by control bits UCPHAn and UCPOLn. The data transfer timing diagrams are
shown in
signal, ensuring sufficient time for data signals to stabilize. The UCPOLn and UCPHAn function-
ality is summarized in
all ongoing communication for both the Receiver and Transmitter.
Figure 19-1. UCPHAn and UCPOLn data transfer timing diagrams.
0
1
0
1
BAUD
f
UBRRn
OSC
Data setup (TXD)
Data sample (RXD)
Data setup (TXD)
XCK
XCK
Data sample (RXD)
1. The baud rate is defined to be the transfer rate in bit per second (bps)
Equation for Calculating Baud Rate
Figure
BAUD
19-1. Data bits are shifted out and latched in on opposite edges of the XCKn
SPI Mode
=
Table
Baud rate (in bits per second, bps)
System Oscillator clock frequency
Contents of the UBRRnH and UBRRnL Registers, (0-4095)
0
1
2
3
UCPOL=0
-------------------------------------- -
2 UBRRn
(
19-2. Note that changing the setting of any of these bits will corrupt
f
OSC
Leading Edge
Sample (Rising)
Setup (Rising)
Sample (Falling)
Setup (Falling)
+
1
)
(1)
ATmega8U2/16U2/32U2
Data setup (TXD)
Data sample (RXD)
Data setup (TXD)
Data sample (RXD)
XCK
XCK
Equation for Calculating UBRRn Value
UBRRn
Setup (Falling)
Sample (Falling)
Setup (Rising)
Sample (Rising)
Trailing Edge
UCPOL=1
=
------------------- - 1
2BAUD
f
OSC
–
177
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