ATmega32U2 Atmel Corporation, ATmega32U2 Datasheet - Page 185
ATmega32U2
Manufacturer Part Number
ATmega32U2
Description
Manufacturer
Atmel Corporation
Specifications of ATmega32U2
Flash (kbytes)
32 Kbytes
Pin Count
32
Max. Operating Frequency
16 MHz
Cpu
8-bit AVR
# Of Touch Channels
12
Hardware Qtouch Acquisition
No
Max I/o Pins
22
Ext Interrupts
20
Usb Transceiver
1
Usb Speed
Full Speed
Usb Interface
Device
Spi
2
Uart
1
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Analog Comparators
1
Resistive Touch Screen
No
Temp. Sensor
No
Crypto Engine
No
Sram (kbytes)
1
Eeprom (bytes)
1024
Self Program Memory
YES
Dram Memory
No
Nand Interface
No
Picopower
No
Temp. Range (deg C)
-40 to 85
I/o Supply Class
2.7 to 5.5
Operating Voltage (vcc)
2.7 to 5.5
Fpu
No
Mpu / Mmu
no / no
Timers
2
Output Compare Channels
5
Input Capture Channels
1
Pwm Channels
4
32khz Rtc
No
Calibrated Rc Oscillator
Yes
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20. USB Controller
20.1
20.2
7799D–AVR–11/10
Features
Overview
•
•
•
The USB controller provides the hardware to implement a USB2.0 compliant Full-Speed USB
device in the ATmega8U2/16U2/32U2. A simplified block diagram of the USB controller is shown
in
The USB controller requires a 48 MHz ±0.25% reference clock for USB Full-Speed compliance.
This clock is generated by an internal PLL. The reference clock to the PLL must be provided
from an external crystal or an external clock input. Only these two clock options will be able to
provide a reference clock within the accuracy and jitter requirements of the USB specification.
S e e s e c t i o n
ATmega8U2/16U2/32U2 system clock and clock options.
To comply to the USB specifications electrical characteristics, the USB Pads (D+ or D-) must be
powered at 3.0V to 3.6V. As the ATmega8U2/16U2/32U2 can be powered up to 5.5V, an inter-
nal regulator is provided to correctly power the USB pads. See
on page 186
Figure 20-1. USB controller Block Diagram
USB 2.0 Full-speed device
Ping-pong mode (dual bank), with transparent switch
176 bytes of DPRAM
Figure 20-1 on page
– 1 endpoint of 64 bytes max (default control endpoint)
– 2 endpoints of 64 bytes max (one bank)
– 2 endpoints of 64 bytes max (one or two banks)
for details on the powering options available for the USB controller
“ S y s t e m C l o c k a n d C l o c k O p t i o n s ” o n p a g e 2 6
UCAP
D-
D+
185.
Recovery
Regulator
DPLL
Clock
UVCC
Interface
USB
clk
48MHz
ATmega8U2/16U2/32U2
PLL
6x
clk
8MHz
“USB Module Powering Options”
USB DPRAM
PLL clock
Prescaler
On-Chip
XTAL1
CPU
f o r d e t a i l s o n t h e
185
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