ATmega32U2 Atmel Corporation, ATmega32U2 Datasheet - Page 197
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ATmega32U2
Manufacturer Part Number
ATmega32U2
Description
Manufacturer
Atmel Corporation
Specifications of ATmega32U2
Flash (kbytes)
32 Kbytes
Pin Count
32
Max. Operating Frequency
16 MHz
Cpu
8-bit AVR
# Of Touch Channels
12
Hardware Qtouch Acquisition
No
Max I/o Pins
22
Ext Interrupts
20
Usb Transceiver
1
Usb Speed
Full Speed
Usb Interface
Device
Spi
2
Uart
1
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Analog Comparators
1
Resistive Touch Screen
No
Temp. Sensor
No
Crypto Engine
No
Sram (kbytes)
1
Eeprom (bytes)
1024
Self Program Memory
YES
Dram Memory
No
Nand Interface
No
Picopower
No
Temp. Range (deg C)
-40 to 85
I/o Supply Class
2.7 to 5.5
Operating Voltage (vcc)
2.7 to 5.5
Fpu
No
Mpu / Mmu
no / no
Timers
2
Output Compare Channels
5
Input Capture Channels
1
Pwm Channels
4
32khz Rtc
No
Calibrated Rc Oscillator
Yes
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21. USB Device Operating modes
21.1
21.2
21.3
7799D–AVR–11/10
Overview
Power-on and reset
Endpoint reset
The USB device controller supports full speed data transfers. In addition to the default control
endpoint, it provides four other endpoints, which can be configured in control, bulk, interrupt or
isochronous modes:
The controller starts in the “idle” mode. In this mode, the pad consumption is reduced to the
minimum.
The next diagram explains the USB device controller main states on power-on:
Figure 21-1. USB device controller states after reset
The reset state of the Device controller is:
The D+ pull-up will be activated as soon as the DETACH bit is cleared.
The macro is in the ‘Idle’ state after reset with a minimum power consumption and does not
need to have the PLL activated to enter in this state.
The USB device controller can at any time be reset by clearing USBE.
An endpoint can be reset at any time by setting in the UERST register the bit corresponding to
the endpoint (EPRSTx). This resets:
• the macro clock is stopped in order to minimize the power consumption (FRZCLK set),
• the USB device controller internal state is reset (all the registers are reset to their default
• the endpoint banks are reset
• the D+ pull up are not activated (mode Detach)
• the internal state machine on that endpoint,
• Endpoint 0:
• Endpoint 1 and 2:
• Endpoint 3 and 4:
value. Note that DETACH is set.)
Programmable size FIFO up to 64 bytes, default control endpoint
Programmable size FIFO up to 64 bytes.
Programmable size FIFO up to 64 bytes with ping-pong mode.
RESET
HW
USBE=0
Reset
USBE=0
state>
<any
other
USBE=1
UID=1
ATmega8U2/16U2/32U2
Idle
197
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