ATmega32U2 Atmel Corporation, ATmega32U2 Datasheet - Page 81

• Manufacturer Part Number: ATmega32U2
• Manufacturer: Atmel Corporation

Specifications of ATmega32U2

• Flash (kbytes): 32 Kbytes
• Pin Count: 32
• Max. Operating Frequency: 16 MHz
• Cpu: 8-bit AVR
• # Of Touch Channels: 12
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 22
• Ext Interrupts: 20
• Usb Transceiver: 1
• Usb Speed: Full Speed
• Usb Interface: Device
• Spi: 2
• Uart: 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Analog Comparators: 1
• Resistive Touch Screen: No
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 1
• Eeprom (bytes): 1024
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: No
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 2.7 to 5.5
• Operating Voltage (vcc): 2.7 to 5.5
• Fpu: No
• Mpu / Mmu: no / no
• Timers: 2
• Output Compare Channels: 5
• Input Capture Channels: 1
• Pwm Channels: 4
• 32khz Rtc: No
• Calibrated Rc Oscillator: Yes

7799D–AVR–11/10
Table 12-10. Overriding Signals for Alternate Functions PD7..PD4
Table 12-11. Overriding Signals for Alternate Functions in PD3..PD0
Note:
Signal Name
PUOE
PUOV
DDOE
DDOV
PVOE
PVOV
DIEOE
DIEOV
DI
AIO
Signal Name
PUOE
PUOV
DDOE
DDOV
PVOE
PVOV
DIEOE
DIEOV
DI
AIO
1. When enabled, the 2-wire Serial Interface enables Slew-Rate controls on the output pins PD0
and PD1. This is not shown in this table. In addition, spike filters are connected between the
AIO outputs shown in the port figure.
PD3/INT3/TXD1
TXEN1
0
TXEN1
1
TXEN1
TXD1
INT3 ENABLE
1
INT3 INPUT
–
PD7/T0/INT7/
HBW/CTS
CTS
PORTD7 •
PUD
CTS
0
0
0
INT7/CTS
ENABLE
1
T0 INPUT
INT7 INPUT
CTS INPUT
–
PD6/INT6/
RTS
RTS
0
RTS
1
RTS
OUTPUT
ENABLE
RTS
OUTPUT
INT6
ENABLE
1
INT6 INPUT
–
PD2/INT2/RXD1/
AIN1
RXEN1
PORTD2 • PUD
RXEN1
0
0
0
INT2 ENABLE
AIN1 ENABLE
AIN1 ENABLE
INT2 INPUT/RXD1
AIN1 INPUT
PD5/XCK/PCINT12
0
0
0
0
XCK OUTPUT ENABLE
XCK1 OUTPUT
PCINT12 ENABLE
1
XCK INPUT
PCINT12 INPUT
–
ATmega8U2/16U2/32U2
PD1/INT1/AIN0
0
0
0
0
0
0
INT1 ENABLE
AIN0 ENABLE
AIN0 ENABLE
INT1 INPUT
AIN0 INPUT
(1)
PD0/INT0/OC0B
0
0
0
0
OC0B ENABLE
OC0B
INT0 ENABLE
1
INT0 INPUT
–
PD4/INT5
0
0
0
0
0
0
INT5
ENABLE
1
INT5 INPUT
–
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