ATmega32U2 Atmel Corporation, ATmega32U2 Datasheet - Page 205
ATmega32U2
Manufacturer Part Number
ATmega32U2
Description
Manufacturer
Atmel Corporation
Specifications of ATmega32U2
Flash (kbytes)
32 Kbytes
Pin Count
32
Max. Operating Frequency
16 MHz
Cpu
8-bit AVR
# Of Touch Channels
12
Hardware Qtouch Acquisition
No
Max I/o Pins
22
Ext Interrupts
20
Usb Transceiver
1
Usb Speed
Full Speed
Usb Interface
Device
Spi
2
Uart
1
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Analog Comparators
1
Resistive Touch Screen
No
Temp. Sensor
No
Crypto Engine
No
Sram (kbytes)
1
Eeprom (bytes)
1024
Self Program Memory
YES
Dram Memory
No
Nand Interface
No
Picopower
No
Temp. Range (deg C)
-40 to 85
I/o Supply Class
2.7 to 5.5
Operating Voltage (vcc)
2.7 to 5.5
Fpu
No
Mpu / Mmu
no / no
Timers
2
Output Compare Channels
5
Input Capture Channels
1
Pwm Channels
4
32khz Rtc
No
Calibrated Rc Oscillator
Yes
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21.14 IN endpoint management
21.14.0.1
7799D–AVR–11/10
“Manual” mode
If the endpoint uses 2 banks, the second one can be filled by the HOST while the current one is
being read by the CPU. Then, when the CPU clear FIFOCON, the next bank may be already
ready and RXOUTI is set immediately.
IN packets are sent by the USB device controller, upon an IN request from the host. All the data
can be written by the CPU, which acknowledge or not the bank when it is full.Overview
The Endpoint must be configured first.
The TXINI bit is set by hardware when the current bank becomes free. This triggers an interrupt
if the TXINE bit is set. The FIFOCON bit is set at the same time. The CPU writes into the FIFO
and clears the FIFOCON bit to allow the USB controller to send the data. If the IN Endpoint is
composed of multiple banks, this also switches to the next data bank. The TXINI and FIFOCON
bits are automatically updated by hardware regarding the status of the next bank.
TXINI shall always be cleared before clearing FIFOCON.
• The CPU can free the bank by clearing FIFOCON when all the data is read, that is:
• after “N” read of UEDATX,
• as soon as RWAL is cleared by hardware.
ATmega8U2/16U2/32U2
205
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