ATmega32U2 Atmel Corporation, ATmega32U2 Datasheet - Page 220
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ATmega32U2
Manufacturer Part Number
ATmega32U2
Description
Manufacturer
Atmel Corporation
Specifications of ATmega32U2
Flash (kbytes)
32 Kbytes
Pin Count
32
Max. Operating Frequency
16 MHz
Cpu
8-bit AVR
# Of Touch Channels
12
Hardware Qtouch Acquisition
No
Max I/o Pins
22
Ext Interrupts
20
Usb Transceiver
1
Usb Speed
Full Speed
Usb Interface
Device
Spi
2
Uart
1
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Analog Comparators
1
Resistive Touch Screen
No
Temp. Sensor
No
Crypto Engine
No
Sram (kbytes)
1
Eeprom (bytes)
1024
Self Program Memory
YES
Dram Memory
No
Nand Interface
No
Picopower
No
Temp. Range (deg C)
-40 to 85
I/o Supply Class
2.7 to 5.5
Operating Voltage (vcc)
2.7 to 5.5
Fpu
No
Mpu / Mmu
no / no
Timers
2
Output Compare Channels
5
Input Capture Channels
1
Pwm Channels
4
32khz Rtc
No
Calibrated Rc Oscillator
Yes
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21.18.16 UEIENX – USB Endpoint Interrupt Enable Register
7799D–AVR–11/10
This flag is set by the USB controller when the current bank contains a new packet. This
RXOUTI flag can generate a “USB endpoint interrupt” if RXOUTE bit is set. Writing this bit to
zero acknowledges the interrupt source (USB clocks must be enabled before). Writing this bit to
one has no effect for an OUT endpoint.
Writing this bit to one kills the last loaded bank. This sequence can be used to cancelled a previ-
ously loaded endpoint. Clearing by software has no effect. See
Abort.
• Bit 1 – STALLEDI: STALLEDI Interrupt Flag
This flag is set by the USB controller when STALL handshake has been sent, or when a CRC
error has been detected for an isochronous OUT endpoint. This STALLEDI flag can generate a
“USB endpoint interrupt” if STALLEDE bit is set. Writing this bit to zero acknowledges the inter-
rupt source (USB clocks must be enabled before). Writing this bit to one has no effect.
• Bit 0 – TXINI: Transmitter Ready Interrupt Flag
This flag is set by the USB controller when the current bank is free and can be filled. This TXINI
flag can generate a “USB endpoint interrupt” if TXINE bit is set. Writing this bit to zero acknowl-
edges the interrupt source (USB clocks must be enabled before). Writing this bit to one has no
effect.
• Bit 7 – FLERRE: Flow Error Interrupt Enable Flag
Writing this bit to one enables interrupt on OVERFI or UNDERFI flags. An overflow or underflow
interrupt will be generated only if the FLERRE bit is set to one, the Global Interrupt Flag in SREG
is written to one, and the OVERFI or UNDERFI flags are set.
• Bit 6 – NAKINE: NAK IN Interrupt Enable Bit
Writing this bit to one enables interrupt on NAKINI flag. A NAK IN interrupt will be generated only
if the NAKINE bit is set to one, the Global Interrupt Flag in SREG is written to one, and the
NAKINI is set.
• Bit 5 – Res: Reserved
This bit is reserved and will always read as zero.
• Bit 4 – NAKOUTE: NAK OUT Interrupt Enable Bit
Writing this bit to one enables interrupt on NAKOUTI flag. A NAKOUT interrupt will be generated
only if the NAKOUTE bit is set to one, the Global Interrupt Flag in SREG is written to one, and
the NAKOUTI is set.
Bit
(0xF0)
Read/Write
Initial Value
• Endpoint IN direction (KILLBK bit)
FLERRE
R/W
7
0
NAKINE
R/W
6
0
R
5
0
-
NAKOUTE
R/W
4
0
RXSTPE
ATmega8U2/16U2/32U2
R/W
3
0
RXOUTE
R/W
2
0
page 206
STALLEDE
R/W
1
0
for more details on the
TXINE
R/W
0
0
UEIENX
220
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