ATmega6450P Atmel Corporation, ATmega6450P Datasheet - Page 186

• Manufacturer Part Number: ATmega6450P
• Manufacturer: Atmel Corporation

Specifications of ATmega6450P

• Flash (kbytes): 64 Kbytes
• Pin Count: 100
• Max. Operating Frequency: 20 MHz
• Cpu: 8-bit AVR
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 69
• Ext Interrupts: 25
• Usb Speed: No
• Usb Interface: No
• Spi: 2
• Twi (i2c): 1
• Uart: 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 8
• Adc Resolution (bits): 10
• Adc Speed (ksps): 15
• Analog Comparators: 1
• Resistive Touch Screen: No
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 4
• Eeprom (bytes): 2048
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: No
• Picopower: Yes
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.8 to 5.5
• Operating Voltage (vcc): 1.8 to 5.5
• Fpu: No
• Mpu / Mmu: no / no
• Timers: 3
• Output Compare Channels: 4
• Input Capture Channels: 1
• Pwm Channels: 4
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

20.8.3
8285D–AVR–06/11
Asynchronous Operational Range
ATmega165A/PA/325A/PA/3250A/PA/645A/P/6450A/P
Figure 20-6. Sampling of Data and Parity Bit
The decision of the logic level of the received bit is taken by doing a majority voting of the logic
value to the three samples in the center of the received bit. The center samples are emphasized
on the figure by having the sample number inside boxes. The majority voting process is done as
follows: If two or all three samples have high levels, the received bit is registered to be a logic 1.
If two or all three samples have low levels, the received bit is registered to be a logic 0. This
majority voting process acts as a low pass filter for the incoming signal on the RxD pin. The
recovery process is then repeated until a complete frame is received. Including the first stop bit.
Note that the Receiver only uses the first stop bit of a frame.
Figure 20-7 on page 186
of the start bit of the next frame.
Figure 20-7. Stop Bit Sampling and Next Start Bit Sampling
The same majority voting is done to the stop bit as done for the other bits in the frame. If the stop
bit is registered to have a logic 0 value, the Frame Error (FEn) Flag will be set.
A new high to low transition indicating the start bit of a new frame can come right after the last of
the bits used for majority voting. For Normal Speed mode, the first low level sample can be at
point marked (A) in
delayed to (B). (C) marks a stop bit of full length. The early start bit detection influences the
operational range of the Receiver.
The operational range of the Receiver is dependent on the mismatch between the received bit
rate and the internally generated baud rate. If the Transmitter is sending frames at too fast or too
slow bit rates, or the internally generated baud rate of the Receiver does not have a similar (see
Table 20-2 on page
frames to the start bit.
The following equations can be used to calculate the ratio of the incoming data rate and internal
receiver baud rate.
(U2X = 0)
(U2X = 1)
(U2X = 0)
(U2X = 1)
Sample
Sample
Sample
Sample
RxD
RxD
R
slow
=
Figure 20-7 on page
------------------------------------------ -
S 1
187) base frequency, the Receiver will not be able to synchronize the
–
1
1
1
1
(
D
+
shows the sampling of the stop bit and the earliest possible beginning
2
2
+
D S ⋅
1
)S
3
2
3
2
+
S
4
4
F
5
3
5
3
186. For Double Speed mode the first low level must be
6
6
7
4
7
4
8
8
STOP 1
BIT n
9
5
9
5
10
10
0/1
(A)
11
6
6
R
0/1
12
fast
0/1
0/1
(B)
13
7
=
14
-----------------------------------
(
D
(
15
+
8
D
1
+
16
)S
2
)S
+
(C)
1
1
S
M
186