ATmega6450P Atmel Corporation, ATmega6450P Datasheet - Page 676

• Manufacturer Part Number: ATmega6450P
• Manufacturer: Atmel Corporation

Specifications of ATmega6450P

• Flash (kbytes): 64 Kbytes
• Pin Count: 100
• Max. Operating Frequency: 20 MHz
• Cpu: 8-bit AVR
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 69
• Ext Interrupts: 25
• Usb Speed: No
• Usb Interface: No
• Spi: 2
• Twi (i2c): 1
• Uart: 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 8
• Adc Resolution (bits): 10
• Adc Speed (ksps): 15
• Analog Comparators: 1
• Resistive Touch Screen: No
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 4
• Eeprom (bytes): 2048
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: No
• Picopower: Yes
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.8 to 5.5
• Operating Voltage (vcc): 1.8 to 5.5
• Fpu: No
• Mpu / Mmu: no / no
• Timers: 3
• Output Compare Channels: 4
• Input Capture Channels: 1
• Pwm Channels: 4
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

8285D–AVR–06/11
ATmega165A/PA/325A/PA/3250A/PA/645A/P/6450A/P
23 ADC - Analog to Digital Converter ..................................................... 214
24 JTAG Interface and On-chip Debug System ..................................... 232
25 IEEE 1149.1 (JTAG) Boundary-scan ................................................... 239
26 Boot Loader Support – Read-While-Write Self-Programming ......... 266
22.2Register Description ............................................................................................212
23.1Features ..............................................................................................................214
23.2Overview .............................................................................................................214
23.3Operation .............................................................................................................215
23.4Starting a Conversion ..........................................................................................216
23.5Prescaling and Conversion Timing ......................................................................217
23.6Changing Channel or Reference Selection .........................................................219
23.7ADC Noise Canceler ...........................................................................................220
23.8ADC Conversion Result ......................................................................................225
23.9Register Description ............................................................................................227
24.1Features ..............................................................................................................232
24.2Overview .............................................................................................................232
24.3TAP – Test Access Port ......................................................................................233
24.4TAP Controller .....................................................................................................235
24.5Using the Boundary-scan Chain ..........................................................................236
24.6Using the On-chip Debug System .......................................................................236
24.7On-chip Debug Specific JTAG Instructions .........................................................237
24.8Using the JTAG Programming Capabilities .........................................................237
24.9On-chip Debug Related Register in I/O Memory .................................................238
24.10Bibliography .......................................................................................................238
25.1Features ..............................................................................................................239
25.2System Overview ................................................................................................239
25.3Data Registers .....................................................................................................240
25.4Boundary-scan Specific JTAG Instructions .........................................................241
25.5Boundary-scan Chain ..........................................................................................242
25.6Boundary-scan Order ..........................................................................................251
25.7Boundary-scan Description Language Files ........................................................264
25.8Boundary-scan Related Register in I/O Memory .................................................265
26.1Features ..............................................................................................................266
26.2Overview .............................................................................................................266
26.3Application and Boot Loader Flash Sections .......................................................266
v