ATmega6450P Atmel Corporation, ATmega6450P Datasheet - Page 245

• Manufacturer Part Number: ATmega6450P
• Manufacturer: Atmel Corporation

Specifications of ATmega6450P

• Flash (kbytes): 64 Kbytes
• Pin Count: 100
• Max. Operating Frequency: 20 MHz
• Cpu: 8-bit AVR
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 69
• Ext Interrupts: 25
• Usb Speed: No
• Usb Interface: No
• Spi: 2
• Twi (i2c): 1
• Uart: 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 8
• Adc Resolution (bits): 10
• Adc Speed (ksps): 15
• Analog Comparators: 1
• Resistive Touch Screen: No
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 4
• Eeprom (bytes): 2048
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: No
• Picopower: Yes
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.8 to 5.5
• Operating Voltage (vcc): 1.8 to 5.5
• Fpu: No
• Mpu / Mmu: no / no
• Timers: 3
• Output Compare Channels: 4
• Input Capture Channels: 1
• Pwm Channels: 4
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

25.5.2
25.5.3
8285D–AVR–06/11
Scanning the RESET Pin
Scanning the Clock Pins
ATmega165A/PA/325A/PA/3250A/PA/645A/P/6450A/P
The RESET pin accepts 5V active low logic for standard reset operation, and 12V active high
logic for High Voltage Parallel programming. An observe-only cell as shown in
page 245
Figure 25-5. Observe-only Cell
The AVR devices have many clock options selectable by fuses. These are: Internal RC Oscilla-
tor, External Clock, (High Frequency) Crystal Oscillator, Low-frequency Crystal Oscillator, and
Ceramic Resonator.
Figure 25-6 on page 245
scan chain. The Enable signal is supported with a general Boundary-scan cell, while the Oscilla-
tor/clock output is attached to an observe-only cell. In addition to the main clock, the timer
Oscillator is scanned in the same way. The output from the internal RC Oscillator is not scanned,
as this Oscillator does not have external connections.
Figure 25-6. Boundary-scan Cells for Oscillators and Clock Options
From Digital Logic
is inserted both for the 5V reset signal; RSTT, and the 12V reset signal; RSTHV.
Previous
From
Cell
From System Pin
ShiftDR
0
1
ClockDR
shows how each Oscillator with external connection is supported in the
D
UpdateDR
Q
Next
Cell
To
Previous
D
G
From
Cell
Q
ShiftDR
EXTEST
0
1
0
1
XTAL1/TOSC1
ClockDR
ENABLE
Oscillator
D
FF1
XTAL2/TOSC2
Q
OUTPUT
Next
Cell
To
Previous
From
To System Logic
Cell
ShiftDR
0
1
ClockDR
D
FF1
Q
Next
Cell
To
Figure 25-5 on
To System Logic
245