ATmega64C1 Automotive Atmel Corporation, ATmega64C1 Automotive Datasheet - Page 118

• Manufacturer Part Number: ATmega64C1 Automotive
• Manufacturer: Atmel Corporation

Specifications of ATmega64C1 Automotive

• Flash (kbytes): 64 Kbytes
• Pin Count: 32
• Max. Operating Frequency: 16 MHz
• Cpu: 8-bit AVR
• # Of Touch Channels: 12
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 27
• Ext Interrupts: 27
• Usb Speed: No
• Usb Interface: No
• Spi: 1
• Uart: 1
• Can: 1
• Lin: 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 11
• Adc Resolution (bits): 10
• Adc Speed (ksps): 125
• Analog Comparators: 4
• Resistive Touch Screen: No
• Dac Channels: 1
• Dac Resolution (bits): 10
• Temp. Sensor: Yes
• Crypto Engine: No
• Sram (kbytes): 4
• Eeprom (bytes): 2048
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: No
• Picopower: No
• Temp. Range (deg C): -40 to 150
• I/o Supply Class: 2.7 to 5.5
• Operating Voltage (vcc): 2.7 to 5.5
• Fpu: No
• Mpu / Mmu: no / no
• Timers: 2
• Output Compare Channels: 4
• Input Capture Channels: 1
• Pwm Channels: 4
• 32khz Rtc: No
• Calibrated Rc Oscillator: Yes

13.6.2
13.6.3
13.7
118
Compare Match Output Unit
Atmel ATmega16/32/64/M1/C1
Compare Match Blocking by TCNTn Write
Using the Output Compare Unit
All CPU writes to the TCNTn Register will block any compare match that occurs in the next
timer clock cycle, even when the timer is stopped. This feature allows OCRnx to be initialized
to the same value as TCNTn without triggering an interrupt when the Timer/Counter clock is
enabled.
Since writing TCNTn in any mode of operation will block all compare matches for one timer
clock cycle, there are risks involved when changing TCNTn when using any of the Output
Compare channels, independent of whether the Timer/Counter is running or not. If the value
written to TCNTn equals the OCRnx value, the compare match will be missed, resulting in
incorrect waveform generation. Do not write the TCNTn equal to TOP in PWM modes with
variable TOP values. The compare match for the TOP will be ignored and the counter will con-
tinue to 0xFFFF. Similarly, do not write the TCNTn value equal to BOTTOM when the counter
is downcounting.
The setup of the OCnx should be performed before setting the Data Direction Register for the
port pin to output. The easiest way of setting the OCnx value is to use the Force Output Com-
pare (FOCnx) strobe bits in Normal mode. The OCnx Register keeps its value even when
changing between Waveform Generation modes.
Be aware that the COMnx1:0 bits are not double buffered together with the compare value.
Changing the COMnx1:0 bits will take effect immediately.
The Compare Output mode (COMnx1:0) bits have two functions. The Waveform Generator
uses the COMnx1:0 bits for defining the Output Compare (OCnx) state at the next compare
match. Secondly the COMnx1:0 bits control the OCnx pin output source.
simplified schematic of the logic affected by the COMnx1:0 bit setting. The I/O Registers, I/O
bits, and I/O pins in the figure are shown in bold. Only the parts of the general I/O Port Control
Registers (DDR and PORT) that are affected by the COMnx1:0 bits are shown. When referring
to the OCnx state, the reference is for the internal OCnx Register, not the OCnx pin. If a sys-
tem reset occur, the OCnx Register is reset to “0”.
Figure 13-5
7647G–AVR–09/11
shows a