ATmega64C1 Automotive Atmel Corporation, ATmega64C1 Automotive Datasheet - Page 36

• Manufacturer Part Number: ATmega64C1 Automotive
• Manufacturer: Atmel Corporation

Specifications of ATmega64C1 Automotive

• Flash (kbytes): 64 Kbytes
• Pin Count: 32
• Max. Operating Frequency: 16 MHz
• Cpu: 8-bit AVR
• # Of Touch Channels: 12
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 27
• Ext Interrupts: 27
• Usb Speed: No
• Usb Interface: No
• Spi: 1
• Uart: 1
• Can: 1
• Lin: 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 11
• Adc Resolution (bits): 10
• Adc Speed (ksps): 125
• Analog Comparators: 4
• Resistive Touch Screen: No
• Dac Channels: 1
• Dac Resolution (bits): 10
• Temp. Sensor: Yes
• Crypto Engine: No
• Sram (kbytes): 4
• Eeprom (bytes): 2048
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: No
• Picopower: No
• Temp. Range (deg C): -40 to 150
• I/o Supply Class: 2.7 to 5.5
• Operating Voltage (vcc): 2.7 to 5.5
• Fpu: No
• Mpu / Mmu: no / no
• Timers: 2
• Output Compare Channels: 4
• Input Capture Channels: 1
• Pwm Channels: 4
• 32khz Rtc: No
• Calibrated Rc Oscillator: Yes

5.6.2
5.7
5.8
36
128 kHz Internal Oscillator
External Clock
Atmel ATmega16/32/64/M1/C1
PLL Control and Status Register – PLLCSR
• Bit 7..3 – Res: Reserved Bits
These bits are reserved bits in the ATmega16/32/64/M1/C1 and always read as zero.
• Bit 2 – PLLF: PLL Factor
The PLLF bit is used to select the division factor of the PLL.
If PLLF is set, the PLL output is 64MHz.
If PLLF is clear, the PLL output is 32MHz.
• Bit 1 – PLLE: PLL Enable
When the PLLE is set, the PLL is started and if not yet started the internal RC Oscillator is
started as PLL reference clock. If PLL is selected as a system clock source the value for this
bit is always 1.
• Bit 0 – PLOCK: PLL Lock Detector
When the PLOCK bit is set, the PLL is locked to the reference clock, and it is safe to enable
CLK
lock.
The 128 kHz internal Oscillator is a low power Oscillator providing a clock of 128 kHz. The fre-
quency is nominal at 3V and 25°C. This clock is used by the Watchdog Oscillator.
To drive the device from an external clock source, XTAL1 should be driven as shown in
5-4. To run the device on an external clock, the CKSEL Fuses must be programmed to “0000”.
Figure 5-4.
Table 5-8.
Bit
$29 ($29)
Read/Write
Initial Value
CKSEL3..0
0000
PLL
for Fast Peripherals. After the PLL is enabled, it takes about 100 ms for the PLL to
External Clock Drive Configuration
External Clock Frequency
R
7
–
0
R
6
–
0
External
R
5
–
0
Signal
Clock
NC
Frequency Range
0 - 16MHz
R
4
–
0
R
3
–
0
PLLF
R/W
XTAL2
XTAL1
GND
2
0
PLLE
R/W
0/1
1
PLOCK
R
0
0
7647G–AVR–09/11
PLLCSR
Figure