ATmega64C1 Automotive Atmel Corporation, ATmega64C1 Automotive Datasheet - Page 165

• Manufacturer Part Number: ATmega64C1 Automotive
• Manufacturer: Atmel Corporation

Specifications of ATmega64C1 Automotive

• Flash (kbytes): 64 Kbytes
• Pin Count: 32
• Max. Operating Frequency: 16 MHz
• Cpu: 8-bit AVR
• # Of Touch Channels: 12
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 27
• Ext Interrupts: 27
• Usb Speed: No
• Usb Interface: No
• Spi: 1
• Uart: 1
• Can: 1
• Lin: 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 11
• Adc Resolution (bits): 10
• Adc Speed (ksps): 125
• Analog Comparators: 4
• Resistive Touch Screen: No
• Dac Channels: 1
• Dac Resolution (bits): 10
• Temp. Sensor: Yes
• Crypto Engine: No
• Sram (kbytes): 4
• Eeprom (bytes): 2048
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: No
• Picopower: No
• Temp. Range (deg C): -40 to 150
• I/o Supply Class: 2.7 to 5.5
• Operating Voltage (vcc): 2.7 to 5.5
• Fpu: No
• Mpu / Mmu: no / no
• Timers: 2
• Output Compare Channels: 4
• Input Capture Channels: 1
• Pwm Channels: 4
• 32khz Rtc: No
• Calibrated Rc Oscillator: Yes

15.2.5
7647G–AVR–09/11
SPI Status Register – SPSR
These two bits control the SCK rate of the device configured as a Master. SPR1 and SPR0
have no effect on the Slave. The relationship between SCK and the clk
shown in the following table:
Table 15-4.
• Bit 7 – SPIF: SPI Interrupt Flag
When a serial transfer is complete, the SPIF flag is set. An interrupt is generated if SPIE in
SPCR is set and global interrupts are enabled. If SS is an input and is driven low when the SPI
is in Master mode, this will also set the SPIF flag. SPIF is cleared by hardware when executing
the corresponding interrupt handling vector. Alternatively, the SPIF bit is cleared by first read-
ing the SPI Status Register with SPIF set, then accessing the SPI Data Register (SPDR).
• Bit 6 – WCOL: Write COLlision Flag
The WCOL bit is set if the SPI Data Register (SPDR) is written during a data transfer. The
WCOL bit (and the SPIF bit) are cleared by first reading the SPI Status Register with WCOL
set, and then accessing the SPI Data Register.
• Bit 5..1 – Res: Reserved Bits
These bits are reserved bits in the ATmega16/32/64/M1/C1 and will always read as zero.
• Bit 0 – SPI2X: Double SPI Speed Bit
When this bit is written logic one the SPI speed (SCK Frequency) will be doubled when the
SPI is in Master mode (see
CPU clock periods. When the SPI is configured as Slave, the SPI is only guaranteed to work at
f
The SPI interface on the ATmega16/32/64/M1/C1 is also used for program memory and
EEPROM downloading or uploading. See
gramming and verification.
Bit
Read/Write
Initial Value
clkio
/4 or lower.
SPI2X
0
0
0
0
1
1
1
1
Relationship Between SCK and the Oscillator Frequency
SPIF
R
7
0
WCOL
SPR1
R
6
0
0
0
1
1
0
0
1
1
Table
15-4). This means that the minimum SCK period will be two
R
5
–
0
Atmel ATmega16/32/64/M1/C1
Serial Programming Algorithm313
SPR0
R
4
–
0
0
1
0
1
0
1
0
1
R
3
–
0
SCK Frequency
f
f
f
f
f
f
f
f
clkio
clkio
clkio
clkio
clkio
clkio
clkio
clkio
/
/
/
/
/
/
/
/
4
16
64
128
2
8
32
64
R
2
–
0
R
1
–
0
IO
frequency f
SPI2X
R/W
for serial pro-
0
0
SPSR
clkio
165
is