ATmega64C1 Automotive Atmel Corporation, ATmega64C1 Automotive Datasheet - Page 163

• Manufacturer Part Number: ATmega64C1 Automotive
• Manufacturer: Atmel Corporation

Specifications of ATmega64C1 Automotive

• Flash (kbytes): 64 Kbytes
• Pin Count: 32
• Max. Operating Frequency: 16 MHz
• Cpu: 8-bit AVR
• # Of Touch Channels: 12
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 27
• Ext Interrupts: 27
• Usb Speed: No
• Usb Interface: No
• Spi: 1
• Uart: 1
• Can: 1
• Lin: 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 11
• Adc Resolution (bits): 10
• Adc Speed (ksps): 125
• Analog Comparators: 4
• Resistive Touch Screen: No
• Dac Channels: 1
• Dac Resolution (bits): 10
• Temp. Sensor: Yes
• Crypto Engine: No
• Sram (kbytes): 4
• Eeprom (bytes): 2048
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: No
• Picopower: No
• Temp. Range (deg C): -40 to 150
• I/o Supply Class: 2.7 to 5.5
• Operating Voltage (vcc): 2.7 to 5.5
• Fpu: No
• Mpu / Mmu: no / no
• Timers: 2
• Output Compare Channels: 4
• Input Capture Channels: 1
• Pwm Channels: 4
• 32khz Rtc: No
• Calibrated Rc Oscillator: Yes

15.2
15.2.1
15.2.2
15.2.3
7647G–AVR–09/11
SS Pin Functionality
Slave Mode
Master Mode
MCU Control Register – MCUCR
When the SPI is configured as a Slave, the Slave Select (SS) pin is always input. When SS is
held low, the SPI is activated, and MISO becomes an output if configured so by the user. All
other pins are inputs. When SS is driven high, all pins are inputs, and the SPI is passive, which
means that it will not receive incoming data. Note that the SPI logic will be reset once the SS
pin is driven high.
The SS pin is useful for packet/byte synchronization to keep the slave bit counter synchronous
with the master clock generator. When the SS pin is driven high, the SPI slave will immediately
reset the send and receive logic, and drop any partially received data in the Shift Register.
When the SPI is configured as a Master (MSTR in SPCR is set), the user can determine the
direction of the SS pin.
If SS is configured as an output, the pin is a general output pin which does not affect the SPI
system. Typically, the pin will be driving the SS pin of the SPI Slave.
If SS is configured as an input, it must be held high to ensure Master SPI operation. If the SS
pin is driven low by peripheral circuitry when the SPI is configured as a Master with the SS pin
defined as an input, the SPI system interprets this as another master selecting the SPI as a
slave and starting to send data to it. To avoid bus contention, the SPI system takes the follow-
ing actions:
Thus, when interrupt-driven SPI transmission is used in Master mode, and there exists a pos-
sibility that SS is driven low, the interrupt should always check that the MSTR bit is still set. If
the MSTR bit has been cleared by a slave select, it must be set by the user to re-enable SPI
Master mode.
• Bit 7– SPIPS: SPI Pin Redirection
Thanks to SPIPS (SPI Pin Select) in MCUCR Sfr, SPI pins can be redirected.
Note that programming port are always located on alternate SPI port.
Bit
Read/Write
Initial Value
1. The MSTR bit in SPCR is cleared and the SPI system becomes a Slave. As a result
2. The SPIF flag in SPSR is set, and if the SPI interrupt is enabled, and the I-bit in
• When the SPIPS bit is written to zero, the SPI signals are directed on pins MISO,MOSI,
• When the SPIPS bit is written to one,the SPI signals are directed on alternate SPI pins,
SCK and SS.
MISO_A, MOSI_A, SCK_A and SS_A.
of the SPI becoming a Slave, the MOSI and SCK pins become inputs.
SREG is set, the interrupt routine will be executed.
SPIPS
R/W
7
0
6
–
R
0
R
5
–
0
Atmel ATmega16/32/64/M1/C1
PUD
R/W
4
0
R
3
–
0
R
2
–
0
IVSEL
R/W
1
0
IVCE
R/W
0
0
MCUCR
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