ATmega64C1 Automotive Atmel Corporation, ATmega64C1 Automotive Datasheet - Page 222

• Manufacturer Part Number: ATmega64C1 Automotive
• Manufacturer: Atmel Corporation

Specifications of ATmega64C1 Automotive

• Flash (kbytes): 64 Kbytes
• Pin Count: 32
• Max. Operating Frequency: 16 MHz
• Cpu: 8-bit AVR
• # Of Touch Channels: 12
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 27
• Ext Interrupts: 27
• Usb Speed: No
• Usb Interface: No
• Spi: 1
• Uart: 1
• Can: 1
• Lin: 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 11
• Adc Resolution (bits): 10
• Adc Speed (ksps): 125
• Analog Comparators: 4
• Resistive Touch Screen: No
• Dac Channels: 1
• Dac Resolution (bits): 10
• Temp. Sensor: Yes
• Crypto Engine: No
• Sram (kbytes): 4
• Eeprom (bytes): 2048
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: No
• Picopower: No
• Temp. Range (deg C): -40 to 150
• I/o Supply Class: 2.7 to 5.5
• Operating Voltage (vcc): 2.7 to 5.5
• Fpu: No
• Mpu / Mmu: no / no
• Timers: 2
• Output Compare Channels: 4
• Input Capture Channels: 1
• Pwm Channels: 4
• 32khz Rtc: No
• Calibrated Rc Oscillator: Yes

17.5.15.2
17.5.16
222
Atmel ATmega16/32/64/M1/C1
OCD Support
UART Data Register
The LINDAT register is the data register (no buffering - no FIFO). In write access, LINDAT will
be for data out and in read access, LINDAT will be for data in.
In UART mode the LINSEL register is unused.
This section describes the behavior of the LIN/UART controller stopped by the OCD (i.e. I/O
view behavior in AVR Studio
Note:
1. LINCR:
2. LINSIR:
3. LINENR:
4. LINERR:
5. LINBTR:
6. LINBRRH & LINBRRL:
7. LINDLR:
8. LINIDR:
9. LINSEL:
10. LINDAT:
- LINCR[6..0] are R/W accessible,
- LSWRES always is a self-reset bit (needs 1 micro-controller cycle to execute)
- LIDST[2..0] and LBUSY are always Read accessible,
- LERR & LxxOK bit are directly accessible (unlike in execution, set or cleared directly
by writing 1 or 0).
- Note that clearing LERR resets all LINERR bits and setting LERR sets all LINERR
bits.
- All bits are R/W accessible.
- All bits are R/W accessible,
- Note that LINERR bits are ORed to provide the LERR interrupt flag of LINSIR.
- LBT[5..0] are R/W access only if LDISR is set,
- If LDISR is reset, LBT[5..0] are unchangeable.
- All bits are R/W accessible.
- All bits are R/W accessible.
- LID[5..0] are R/W accessible,
- LP[1..0] are Read accessible and are always updated on the fly.
- All bits are R/W accessible.
- All bits are in R/W accessible,
- Note that LAINC has no more effect on the auto-incrementation and the access to
the full FIFO is done setting LINDX[2..0] of LINSEL.
When a debugger break occurs, the state machine of the LIN/UART controller is stopped
(included frame time-out) and further communication may be corrupted.
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7647G–AVR–09/11