ATmega64C1 Automotive Atmel Corporation, ATmega64C1 Automotive Datasheet - Page 344

• Manufacturer Part Number: ATmega64C1 Automotive
• Manufacturer: Atmel Corporation

Specifications of ATmega64C1 Automotive

• Flash (kbytes): 64 Kbytes
• Pin Count: 32
• Max. Operating Frequency: 16 MHz
• Cpu: 8-bit AVR
• # Of Touch Channels: 12
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 27
• Ext Interrupts: 27
• Usb Speed: No
• Usb Interface: No
• Spi: 1
• Uart: 1
• Can: 1
• Lin: 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 11
• Adc Resolution (bits): 10
• Adc Speed (ksps): 125
• Analog Comparators: 4
• Resistive Touch Screen: No
• Dac Channels: 1
• Dac Resolution (bits): 10
• Temp. Sensor: Yes
• Crypto Engine: No
• Sram (kbytes): 4
• Eeprom (bytes): 2048
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: No
• Picopower: No
• Temp. Range (deg C): -40 to 150
• I/o Supply Class: 2.7 to 5.5
• Operating Voltage (vcc): 2.7 to 5.5
• Fpu: No
• Mpu / Mmu: no / no
• Timers: 2
• Output Compare Channels: 4
• Input Capture Channels: 1
• Pwm Channels: 4
• 32khz Rtc: No
• Calibrated Rc Oscillator: Yes

28. Instruction Set Summary
344
Mnemonics
FMULSU
MULSU
CALL(*)
FMULS
RCALL
JMP(*)
MULS
FMUL
RJMP
ICALL
CPSE
SBRC
SBRS
BRBS
BRBC
BREQ
BRNE
BRCS
BRCC
BRSH
BRLO
BRGE
BRHS
BRHC
BRTC
BRVS
BRVC
ADIW
SBIW
BRPL
BRLT
BRTS
SUBI
SBCI
ANDI
COM
SBIC
BRMI
BRIE
ADD
ADC
AND
EOR
NEG
CBR
DEC
MUL
IJMP
RETI
CPC
SBIS
SUB
SBC
SBR
CLR
SER
RET
ORI
INC
TST
CPI
OR
CP
Atmel ATmega16/32/64/M1/C1
Operands
Rd, Rr
Rd, Rr
Rd, Rr
Rd, Rr
Rd, Rr
Rd, Rr
Rd, Rr
Rd, Rr
Rd, Rr
Rd, Rr
Rd, Rr
Rd, Rr
Rd, Rr
Rd,Rr
Rd,Rr
Rd,Rr
Rdl,K
Rd, K
Rd, K
Rdl,K
Rd, K
Rd, K
Rd,K
Rd,K
Rd,K
Rr, b
Rr, b
P, b
P, b
s, k
s, k
Rd
Rd
Rd
Rd
Rd
Rd
Rd
k
k
k
k
k
k
k
k
k
k
k
k
k
k
k
k
k
k
k
k
k
ARITHMETIC AND LOGIC INSTRUCTIONS
BRANCH INSTRUCTIONS
Fractional Multiply Signed with Unsigned
Subtract with Carry Constant from Reg.
Logical AND Register and Constant
Branch if Greater or Equal, Signed
Logical OR Register and Constant
Compare Register with Immediate
Branch if Overflow Flag is Cleared
Subtract with Carry two Registers
Branch if Less Than Zero, Signed
Skip if Bit in I/O Register Cleared
Branch if Half Carry Flag Cleared
Subtract Constant from Register
Subtract Immediate from Word
Skip if Bit in I/O Register is Set
Multiply Signed with Unsigned
Branch if Status Flag Cleared
Branch if Overflow Flag is Set
Add with Carry two Registers
Skip if Bit in Register Cleared
Branch if Half Carry Flag Set
Fractional Multiply Unsigned
Skip if Bit in Register is Set
Branch if Interrupt Enabled
Fractional Multiply Signed
Branch if Same or Higher
Branch if Status Flag Set
Relative Subroutine Call
Branch if T Flag Cleared
Add Immediate to Word
Exclusive OR Registers
Branch if Carry Cleared
Compare, Skip if Equal
Subtract two Registers
Logical AND Registers
Clear Bit(s) in Register
Test for Zero or Minus
Direct Subroutine Call
Logical OR Registers
Set Bit(s) in Register
Compare with Carry
Branch if T Flag Set
One’s Complement
Two’s Complement
Indirect Jump to (Z)
Branch if Not Equal
Branch if Carry Set
Add two Registers
Indirect Call to (Z)
Subroutine Return
Multiply Unsigned
Interrupt Return
Multiply Signed
Branch if Equal
Branch if Lower
Branch if Minus
Description
Clear Register
Relative Jump
Branch if Plus
Set Register
Direct Jump
Decrement
Increment
Compare
if (SREG(s) = 1) then PC PC+k + 1
if (SREG(s) = 0) then PC PC+k + 1
if (N
if (N
if (C = 1) then PC
if (N = 1) then PC
if (T = 1) then PC
if (Z = 1) then PC
if (Z = 0) then PC
if (C = 1) then PC
if (C = 0) then PC
if (C = 0) then PC
if (N = 0) then PC
if (H = 1) then PC
if (H = 0) then PC
if (T = 0) then PC
if (V = 1) then PC
if (V = 0) then PC
if ( I = 1) then PC
if (Rd = Rr) PC
if (Rr(b)=0) PC
if (Rr(b)=1) PC
if (P(b)=0) PC
if (P(b)=1) PC
R1:R0
R1:R0
R1:R0
Rdh:Rdl
Rdh:Rdl
Rd
V= 0) then PC
V= 1) then PC
Rd
PC
R1:R0
R1:R0
R1:R0
Rd
PC
Rd
Rd
Rd
Rd
Rd
Rd
Rd
Rd
Rd
PC
PC
Rd
Rd
Operation
Rd
Rd
Rd
Rd
Rd
Rd - Rr - C
Rd
Rd · (0xFF - K)
PC
PC
PC
PC
Rd - Rr
Rd + Rr + C
Rd - K
PC + k + 1
Rd - Rr - C
(Rd x Rr) << 1
(Rd x Rr) << 1
(Rd x Rr) << 1
PC + k + 1
Rd - K - C
0xFF - Rd
0x00 - Rd
Rd
Rd
Rd
Rd + Rr
Rd
Rd v Rr
Rd - Rr
STACK
STACK
Rdh:Rdl + K
Rd
Rd v K
Rd v K
Rd + 1
Rd - K
Rdh:Rdl - K
Rd - 1
0xFF
Rd x Rr
Rd x Rr
Rd x Rr
Z
k
Z
k
PC + 2 or 3
PC + 2 or 3
PC + 2 or 3
PC + 2 or 3
PC + 2 or 3
Rd
Rr
Rd
PC + k + 1
Rr
PC + k + 1
PC + k + 1
PC + k + 1
PC + k + 1
PC + k + 1
PC + k + 1
PC + k + 1
PC + k + 1
PC + k + 1
PC + k + 1
PC + k + 1
PC + k + 1
PC + k + 1
PC + k + 1
K
PC + k + 1
PC + k + 1
Z, N,V,C,H
Z, N,V,C,H
Z, N,V,C,H
Z,C,N,V,H
Z,C,N,V,H
Z,C,N,V,S
Z,C,N,V,H
Z,C,N,V,H
Z,C,N,V,H
Z,C,N,V,H
Z,C,N,V,S
Z,C,N,V,H
Z,C,N,V
Flags
Z,N,V
Z,N,V
Z,N,V
Z,N,V
Z,N,V
Z,N,V
Z,N,V
Z,N,V
Z,N,V
Z,N,V
Z,N,V
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
Z,C
Z,C
Z,C
Z,C
Z,C
Z,C
I
7647G–AVR–09/11
#Clocks
1/2/3
1/2/3
1/2/3
1/2/3
1/2/3
1/2
1/2
1/2
1/2
1/2
1/2
1/2
1/2
1/2
1/2
1/2
1/2
1/2
1/2
1/2
1/2
1/2
1/2
1/2
1
1
2
1
1
1
1
2
1
1
1
1
1
1
1
1
1
1
1
1
1
1
2
2
2
2
2
2
2
2
3
3
3
4
4
4
1
1
1