ATtiny26 Atmel Corporation, ATtiny26 Datasheet - Page 40

• Manufacturer Part Number: ATtiny26
• Manufacturer: Atmel Corporation

Specifications of ATtiny26

• Flash (kbytes): 2 Kbytes
• Pin Count: 20
• Max. Operating Frequency: 16 MHz
• Cpu: 8-bit AVR
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 16
• Ext Interrupts: 11
• Usb Speed: No
• Usb Interface: No
• Spi: 1
• Twi (i2c): 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 11
• Adc Resolution (bits): 10
• Adc Speed (ksps): 15
• Analog Comparators: 1
• Resistive Touch Screen: No
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 0.12
• Eeprom (bytes): 128
• Self Program Memory: NO
• Dram Memory: No
• Nand Interface: No
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 2.7 to 5.5
• Operating Voltage (vcc): 2.7 to 5.5
• Fpu: No
• Mpu / Mmu: no / no
• Timers: 2
• Output Compare Channels: 3
• Pwm Channels: 4
• 32khz Rtc: No
• Calibrated Rc Oscillator: Yes

Minimizing Power
Consumption
Analog to Digital
Converter
Analog Comparator
Brown-out Detector
Internal Voltage
Reference
Watchdog Timer
Port Pins
40
ATtiny26(L)
There are several issues to consider when trying to minimize the power consumption in an AVR
controlled system. In general, sleep modes should be used as much as possible, and the sleep
mode should be selected so that as few as possible of the device’s functions are operating. All
functions not needed should be disabled. In particular, the following modules may need special
consideration when trying to achieve the lowest possible power consumption.
If enabled, the ADC will be enabled in all sleep modes. To save power, the ADC should be dis-
abled before entering any sleep mode. When the ADC is turned off and on again, the next
conversion will be an extended conversion. Refer to “Analog to Digital Converter” on page 94 for
details on ADC operation.
When entering Idle mode, the Analog Comparator should be disabled if not used. When entering
ADC Noise Reduction mode, the Analog Comparator should be disabled. In the other sleep
modes, the Analog Comparator is automatically disabled. However, if the Analog Comparator is
set up to use the Internal Voltage Reference as input, the Analog Comparator should be dis-
abled in all sleep modes. Otherwise, the Internal Voltage Reference will be enabled,
independent of sleep mode. Refer to “Analog Comparator” on page 91 for details on how to con-
figure the Analog Comparator.
If the Brown-out Detector is not needed in the application, this module should be turned off. If the
Brown-out Detector is enabled by the BODEN Fuse, it will be enabled in all sleep modes, and
hence, always consume power. In the deeper sleep modes, this will contribute significantly to
the total current consumption. Refer to “Brown-out Detection” on page 35 for details on how to
configure the Brown-out Detector.
The Internal Voltage Reference (see Table 20) will be enabled when needed by the Brown-out
Detector, the Analog Comparator or the ADC. If these modules are disabled as described in the
sections above, the Internal Voltage Reference will be disabled and it will not be consuming
power. When turned on again, the user must allow the reference to start up before the output is
used. If the reference is kept on in sleep mode, the output can be used immediately.
Table 20. Internal Voltage Reference
If the Watchdog Timer is not needed in the application, this module should be turned off. If the
Watchdog Timer is enabled, it will be enabled in all sleep modes, and hence, always consume
power. In the deeper sleep modes, this will contribute significantly to the total current consump-
tion. Refer to “Watchdog Timer” on page 78 for details on how to configure the Watchdog Timer.
When entering a sleep mode, all port pins should be configured to use minimum power. The
most important thing is then to ensure that no pins drive resistive loads. In sleep modes where
the both the I/O clock (clk
device will be disabled. This ensures that no power is consumed by the input logic when not
needed. In some cases, the input logic is needed for detecting wake-up conditions, and it will
then be enabled. Refer to “Digital Input Enable and Sleep Modes” on page 45 for details on
which pins are enabled. If the input buffer is enabled and the input signal is left floating or have
an analog signal level close to V
Symbol
V
t
I
BG
BG
BG
Parameter
Bandgap reference voltage
Bandgap reference start-up time
Bandgap reference current consumption
I/O
) and the ADC clock (clk
CC
/2, the input buffer will use excessive power.
ADC
1.15
Min
) are stopped, the input buffers of the
1.18
Typ
40
10
Max
1.40
70
Units
µA
1477K–AVR–08/10
µs
V