ATtiny26 Atmel Corporation, ATtiny26 Datasheet - Page 92

• Manufacturer Part Number: ATtiny26
• Manufacturer: Atmel Corporation

Specifications of ATtiny26

• Flash (kbytes): 2 Kbytes
• Pin Count: 20
• Max. Operating Frequency: 16 MHz
• Cpu: 8-bit AVR
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 16
• Ext Interrupts: 11
• Usb Speed: No
• Usb Interface: No
• Spi: 1
• Twi (i2c): 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 11
• Adc Resolution (bits): 10
• Adc Speed (ksps): 15
• Analog Comparators: 1
• Resistive Touch Screen: No
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 0.12
• Eeprom (bytes): 128
• Self Program Memory: NO
• Dram Memory: No
• Nand Interface: No
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 2.7 to 5.5
• Operating Voltage (vcc): 2.7 to 5.5
• Fpu: No
• Mpu / Mmu: no / no
• Timers: 2
• Output Compare Channels: 3
• Pwm Channels: 4
• 32khz Rtc: No
• Calibrated Rc Oscillator: Yes

92
ATtiny26(L)
• Bit 4 – ACI: Analog Comparator Interrupt Flag
This bit is set (one) when a comparator output event triggers the interrupt mode defined by ACI1
and ACI0. The Analog Comparator Interrupt routine is executed if the ACIE bit is set (one) and
the I-bit in SREG is set (one). ACI is cleared by hardware when executing the corresponding
interrupt handling vector. Alternatively, ACI is cleared by writing a logic one to the flag.
• Bit 3 – ACIE: Analog Comparator Interrupt Enable
When the ACIE bit is set (one) and the I-bit in the Status Register is set (one), the Analog Com-
parator interrupt is activated. When cleared (zero), the interrupt is disabled.
• Bit 2 – ACME: Analog Comparator Multiplexer Enable
When the ACME bit is set (one) and the ADC is switched off (ADEN in ADCSR is zero),
MUX3...0 in ADMUX select the input pin to replace the negative input to the Analog Comparator,
as shown in Table 42 on page 93. If ACME is cleared (zero) or ADEN is set (one), PA7(AIN1) is
applied to the negative input to the Analog Comparator.
• Bits 1, 0 – ACIS1, ACIS0: Analog Comparator Interrupt Mode Select
These bits determine which comparator events that trigger the Analog Comparator interrupt. The
different settings are shown in Table 41.
Table 41. ACIS1/ACIS0 Settings
Note:
ACIS1
0
0
1
1
1. When changing the ACIS1/ACIS0 bits, the Analog Comparator Interrupt must be disabled by
clearing its Interrupt Enable bit in the ACSR Register. Otherwise an interrupt can occur when
the bits are changed.
ACIS0
0
1
0
1
Interrupt Mode
Comparator Interrupt on Output Toggle
Reserved
Comparator Interrupt on Falling Output Edge
Comparator Interrupt on Rising Output Edge
(1)
1477K–AVR–08/10