ATtiny26 Atmel Corporation, ATtiny26 Datasheet - Page 58

• Manufacturer Part Number: ATtiny26
• Manufacturer: Atmel Corporation

Specifications of ATtiny26

• Flash (kbytes): 2 Kbytes
• Pin Count: 20
• Max. Operating Frequency: 16 MHz
• Cpu: 8-bit AVR
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 16
• Ext Interrupts: 11
• Usb Speed: No
• Usb Interface: No
• Spi: 1
• Twi (i2c): 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 11
• Adc Resolution (bits): 10
• Adc Speed (ksps): 15
• Analog Comparators: 1
• Resistive Touch Screen: No
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 0.12
• Eeprom (bytes): 128
• Self Program Memory: NO
• Dram Memory: No
• Nand Interface: No
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 2.7 to 5.5
• Operating Voltage (vcc): 2.7 to 5.5
• Fpu: No
• Mpu / Mmu: no / no
• Timers: 2
• Output Compare Channels: 3
• Pwm Channels: 4
• 32khz Rtc: No
• Calibrated Rc Oscillator: Yes

Interrupt Handling
Interrupt Response
Time
General Interrupt
Mask Register –
GIMSK
58
ATtiny26(L)
The ATtiny26(L) has two 8-bit Interrupt Mask Control Registers; GIMSK – General Interrupt
Mask Register and TIMSK – Timer/Counter Interrupt Mask Register.
When an interrupt occurs, the Global Interrupt Enable I-bit is cleared (zero) and all interrupts are
disabled. The user software can set (one) the I-bit to enable nested interrupts. The I-bit is set
(one) when a Return from Interrupt instruction – RETI – is executed.
When the Program Counter is vectored to the actual Interrupt Vector in order to execute the
interrupt handling routine, hardware clears the corresponding flag that generated the interrupt.
Some of the interrupt flags can also be cleared by writing a logic one to the flag bit position(s) to
be cleared.
If an interrupt condition occurs when the corresponding interrupt enable bit is cleared (zero), the
interrupt flag will be set and remembered until the interrupt is enabled, or the flag is cleared by
software.
If one or more interrupt conditions occur when the Global Interrupt Enable bit is cleared (zero),
the corresponding interrupt flag(s) will be set and remembered until the Global Interrupt Enable
bit is set (one), and will be executed by order of priority.
Note that external level interrupt does not have a flag, and will only be remembered for as long
as the interrupt condition is active.
Note that the Status Register is not automatically stored when entering an interrupt routine and
restored when returning from an interrupt routine. This must be handled by software.
The interrupt execution response for all the enabled AVR interrupts is four clock cycles mini-
mum. After the four clock cycles the program vector address for the actual interrupt handling
routine is executed. During this four clock cycle period, the Program Counter (10 bits) is pushed
onto the Stack. The vector is a relative jump to the interrupt routine, and this jump takes two
clock cycles. If an interrupt occurs during execution of a multi-cycle instruction, this instruction is
completed before the interrupt is served.
A return from an interrupt handling routine takes four clock cycles. During these four clock
cycles, the Program Counter (10 bits) is popped back from the Stack. When AVR exits from an
interrupt, it will always return to the main program and execute one more instruction before any
pending interrupt is served. Note that the Status Register – SREG – is not handled by the AVR
hardware, neither for interrupts nor for subroutines. For the routines requiring a storage of the
SREG, this must be performed by user software.
• Bit 7 – Res: Reserved Bit
This bit is a reserved bit in the ATtiny26(L) and always reads as zero.
• Bit 6 – INT0: External Interrupt Request 0 Enable
When the INT0 bit is set (one) and the I-bit in the Status Register (SREG) is set (one), the exter-
nal pin interrupt is enabled. The Interrupt Sense Control0 bits 1/0 (ISC01 and ISC00) in the MCU
general Control Register (MCUCR) define whether the external interrupt is activated on rising or
falling edge, on pin change, or low level of the INT0 pin. Activity on the pin will cause an interrupt
request even if INT0 is configured as an output. The corresponding interrupt of External Interrupt
Request 0 is executed from program memory address $001. See also “External Interrupt” on
page 62.
Bit
$3B ($5B)
Read/Write
Initial Value
R
7
–
0
INT0
R/W
6
0
PCIE1
R/W
5
0
PCIE0
R/W
0
4
3
R
0
–
R
2
–
0
R
1
–
0
R
0
–
0
GIMSK
1477K–AVR–08/10