ATtiny26 Atmel Corporation, ATtiny26 Datasheet - Page 43

• Manufacturer Part Number: ATtiny26
• Manufacturer: Atmel Corporation

Specifications of ATtiny26

• Flash (kbytes): 2 Kbytes
• Pin Count: 20
• Max. Operating Frequency: 16 MHz
• Cpu: 8-bit AVR
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 16
• Ext Interrupts: 11
• Usb Speed: No
• Usb Interface: No
• Spi: 1
• Twi (i2c): 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 11
• Adc Resolution (bits): 10
• Adc Speed (ksps): 15
• Analog Comparators: 1
• Resistive Touch Screen: No
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 0.12
• Eeprom (bytes): 128
• Self Program Memory: NO
• Dram Memory: No
• Nand Interface: No
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 2.7 to 5.5
• Operating Voltage (vcc): 2.7 to 5.5
• Fpu: No
• Mpu / Mmu: no / no
• Timers: 2
• Output Compare Channels: 3
• Pwm Channels: 4
• 32khz Rtc: No
• Calibrated Rc Oscillator: Yes

Reading the Pin Value
1477K–AVR–08/10
Table 21 summarizes the control signals for the pin value.
Table 21. Port Pin Configurations
Independent of the setting of Data Direction bit DDxn, the port pin can be read through the
PINxn Register Bit. As shown in Figure 32, the PINxn Register bit and the preceding latch con-
stitute a synchronizer. This is needed to avoid metastability if the physical pin changes value
near the edge of the internal clock, but it also introduces a delay. Figure 33 shows a timing dia-
gram of the synchronization when reading an externally applied pin value. The maximum and
minimum propagation delays are denoted t
Figure 33. Synchronization when Reading an Externally Applied Pin Value
Consider the clock period starting shortly after the first falling edge of the system clock. The latch
is closed when the clock is low, and goes transparent when the clock is high, as indicated by the
shaded region of the “SYNC LATCH” signal. The signal value is latched when the system clock
goes low. It is clocked into the PINxn Register at the succeeding positive clock edge. As indi-
cated by the two arrows t
between ½ and 1½ system clock period depending upon the time of assertion.
When reading back a software assigned pin value, a nop instruction must be inserted as indi-
cated in Figure 34. The out instruction sets the “SYNC LATCH” signal at the positive edge of the
clock. In this case, the delay t
DDxn
0
0
0
1
1
INSTRUCTIONS
SYSTEM CLK
SYNC LATCH
PORTxn
0
1
1
0
1
PINxn
r17
(in MCUCR)
PUD
X
0
1
X
X
pd,max
pd
through the synchronizer is one system clock period.
and t
XXX
Output
Output
Input
Input
Input
I/O
pd,min
, a single signal transition on the pin will be delayed
pd,max
Pull-up
t
pd, max
Yes
No
No
No
No
0x00
and t
XXX
Pxn will source current if ext. pulled
low
Output Low (Sink)
Output High (Source)
Comment
Tri-state (Hi-Z)
Tri-state (Hi-Z)
t
pd,min
pd, min
respectively.
in r17, PINx
0xFF
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