ATtiny26 Atmel Corporation, ATtiny26 Datasheet - Page 85

• Manufacturer Part Number: ATtiny26
• Manufacturer: Atmel Corporation

Specifications of ATtiny26

• Flash (kbytes): 2 Kbytes
• Pin Count: 20
• Max. Operating Frequency: 16 MHz
• Cpu: 8-bit AVR
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 16
• Ext Interrupts: 11
• Usb Speed: No
• Usb Interface: No
• Spi: 1
• Twi (i2c): 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 11
• Adc Resolution (bits): 10
• Adc Speed (ksps): 15
• Analog Comparators: 1
• Resistive Touch Screen: No
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 0.12
• Eeprom (bytes): 128
• Self Program Memory: NO
• Dram Memory: No
• Nand Interface: No
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 2.7 to 5.5
• Operating Voltage (vcc): 2.7 to 5.5
• Fpu: No
• Mpu / Mmu: no / no
• Timers: 2
• Output Compare Channels: 3
• Pwm Channels: 4
• 32khz Rtc: No
• Calibrated Rc Oscillator: Yes

Functional
Descriptions
Three-wire Mode
1477K–AVR–08/10
The USI Three-wire mode is compliant to the Serial Peripheral Interface (SPI) mode 0 and 1, but
does not have the slave select (SS) pin functionality. However, this feature can be implemented
in software if necessary. Pin names used by this mode are: DI, DO, and SCK.
Figure 45. Three-wire Mode Operation, Simplified Diagram
Figure 45 shows two USI units operating in Three-wire mode, one as master and one as slave.
The two shift Registers are interconnected in such way that after eight SCK clocks, the data in
each register are interchanged. The same clock also increments the USI’s 4-bit counter. The
Counter Overflow (interrupt) flag, or USIOIF, can therefore be used to determine when a transfer
is completed. The clock is generated by the master device software by toggling the PB2 pin via
the PORTB Register or by writing a one to the USITC bit in USICR.
Figure 46. Three-wire Mode, Timing Diagram
The Three-wire mode timing is shown in Figure 46. At the top of the figure is a SCK cycle refer-
ence. One bit is shifted into the USI Shift Register (USIDR) for each of these cycles. The SCK
timing is shown for both external clock modes. In external clock mode 0 (USICS0 = 0), DI is
sampled at positive edges, and DO is changed (Data Register is shifted by one) at negative
edges. External clock mode 1 (USICS0 = 1) uses the opposite edges versus mode 0, i.e., sam-
CYCLE
SCK
SCK
SLAVE
MASTER
DO
DI
Bit7
Bit7
( Reference )
Bit6
Bit6
A
Bit5
Bit5
B
MSB
Bit4
Bit4
MSB
C
1
Bit3
Bit3
D
Bit2
Bit2
2
6
6
Bit1
Bit1
Bit0
Bit0
3
5
5
4
4
4
5
3
3
PORTBz
6
2
2
PBx
PBy
PBz
PBx
PBy
PBz
7
1
1
DO
DI
SCK
DO
DI
SCK
LSB
LSB
8
E
85