ATtiny26 Atmel Corporation, ATtiny26 Datasheet - Page 78

• Manufacturer Part Number: ATtiny26
• Manufacturer: Atmel Corporation

Specifications of ATtiny26

• Flash (kbytes): 2 Kbytes
• Pin Count: 20
• Max. Operating Frequency: 16 MHz
• Cpu: 8-bit AVR
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 16
• Ext Interrupts: 11
• Usb Speed: No
• Usb Interface: No
• Spi: 1
• Twi (i2c): 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 11
• Adc Resolution (bits): 10
• Adc Speed (ksps): 15
• Analog Comparators: 1
• Resistive Touch Screen: No
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 0.12
• Eeprom (bytes): 128
• Self Program Memory: NO
• Dram Memory: No
• Nand Interface: No
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 2.7 to 5.5
• Operating Voltage (vcc): 2.7 to 5.5
• Fpu: No
• Mpu / Mmu: no / no
• Timers: 2
• Output Compare Channels: 3
• Pwm Channels: 4
• 32khz Rtc: No
• Calibrated Rc Oscillator: Yes

Watchdog
Timer
Watchdog Timer
Control Register –
WDTCR
78
ATtiny26(L)
The Watchdog Timer is clocked from a separate On-chip Oscillator which runs at 1 MHz. This is
the typical value at V
controlling the Watchdog Timer prescaler, the Watchdog Reset interval can be adjusted from 16
to 2048 ms. The WDR – Watchdog Reset – instruction resets the Watchdog Timer. Eight differ-
ent clock cycle periods can be selected to determine the reset period. If the reset period expires
without another Watchdog Reset, the ATtiny26(L) resets and executes from the Reset Vector.
For timing details on the Watchdog Reset, refer to page 35.
To prevent unintentional disabling of the Watchdog, a special turn-off sequence must be fol-
lowed when the Watchdog is disabled. Refer to the description of the Watchdog Timer Control
Register for details.
Figure 43. Watchdog Timer
• Bits 7..5 – Res: Reserved Bits
These bits are reserved bits in the ATtiny26(L) and will always read as zero.
• Bit 4 – WDCE: Watchdog Change Enable
This bit must be set when the WDE bit is written to logic zero. Otherwise, the Watchdog will not
be disabled. Once written to one, hardware will clear this bit after four clock cycles. Refer to the
description of the WDE bit for a Watchdog disable procedure. In Safety Level 1 and 2, this bit
must also be set when changing the prescaler bits.
• Bit 3 – WDE: Watchdog Enable
When the WDE is set (one) the Watchdog Timer is enabled, and if the WDE is cleared (zero) the
Watchdog Timer function is disabled. WDE can be cleared only when the WDCE bit is set(one).
To disable an enabled Watchdog Timer, the following procedure must be followed:
1. In the same operation, write a logical one to WDCE and WDE. A logical one must be writ-
2. Within the next four clock cycles, write a logical 0 to WDE. This disables the Watchdog.
• Bits 2..0 – WDP2, WDP1, WDP0: Watchdog Timer Prescaler 2, 1, and 0
Bit
$21 ($41)
Read/Write
Initial Value
ten to WDE even though it is set to one before the disable operation starts.
R
7
–
0
CC
WATCHDOG
RESET
= 5V. See characterization data for typical values at other V
R
6
–
0
WDP0
WDP1
WDP2
WDE
Normally 1 MHz
R
5
–
0
WDCE
R/W
4
0
WDE
R/W
3
0
WDP2
R/W
2
0
PRESCLALER
WATCHDOG
MCU RESET
WDP1
R/W
1
0
WDP0
R/W
0
0
WDTCR
1477K–AVR–08/10
CC
levels. By