ATtiny26 Atmel Corporation, ATtiny26 Datasheet - Page 67

• Manufacturer Part Number: ATtiny26
• Manufacturer: Atmel Corporation

Specifications of ATtiny26

• Flash (kbytes): 2 Kbytes
• Pin Count: 20
• Max. Operating Frequency: 16 MHz
• Cpu: 8-bit AVR
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 16
• Ext Interrupts: 11
• Usb Speed: No
• Usb Interface: No
• Spi: 1
• Twi (i2c): 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 11
• Adc Resolution (bits): 10
• Adc Speed (ksps): 15
• Analog Comparators: 1
• Resistive Touch Screen: No
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 0.12
• Eeprom (bytes): 128
• Self Program Memory: NO
• Dram Memory: No
• Nand Interface: No
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 2.7 to 5.5
• Operating Voltage (vcc): 2.7 to 5.5
• Fpu: No
• Mpu / Mmu: no / no
• Timers: 2
• Output Compare Channels: 3
• Pwm Channels: 4
• 32khz Rtc: No
• Calibrated Rc Oscillator: Yes

Timer/Counter0 –
TCNT0
8-bit
Timer/Counter1
1477K–AVR–08/10
The Stop condition provides a Timer Enable/Disable function. The CK down divided modes are
scaled directly from the CK oscillator clock. If the external pin modes are used, the correspond-
ing setup must be performed in the actual Data Direction Control Register (cleared to zero gives
an input pin).
The Timer/Counter0 is implemented as an up-counter with read and write access. If the
Timer/Counter0 is written and a clock source is present, the Timer/Counter0 continues counting
in the timer clock cycle following the write operation.
The Timer/Counter1 has two clocking modes: a synchronous mode and an asynchronous mode.
The synchronous mode uses the system clock (CK) as the clock timebase and asynchronous
mode uses the fast peripheral clock (PCK) as the clock time base. The PCKE bit from the
PLLCSR Register enables the asynchronous mode when it is set (“1”). The Timer/Counter1 gen-
eral operation is described in the asynchronous mode and the operation in the synchronous
mode is mentioned only if there is differences between these two modes. Figure 39 shows
Timer/Counter1 synchronization register block diagram and synchronization delays in between
registers. Note that all clock gating details are not shown in the figure. The Timer/Counter1 Reg-
ister values go through the internal synchronization registers, which cause the input
synchronization delay, before affecting the counter operation. The registers TCCR1A, TCCR1B,
OCR1A, OCR1B, and OCR1C can be read back right after writing the register. The read back
values are delayed for the Timer/Counter1 (TCNT1) Register and flags (OCF1A, OCF1B, and
TOV1), because of the input and output synchronization.
This module features a high resolution and a high accuracy usage with the lower prescaling
opportunities. Timer/Counter1 can also support two accurate, high speed, 8-bit Pulse Width
Modulators using clock speeds up to 64 MHz. In this mode, Timer/Counter1 and the Output
Compare Registers serve as dual stand-alone PWMs with non-overlapping non-inverted and
inverted outputs. Refer to page 74 for a detailed description on this function. Similarly, the high
prescaling opportunities make this unit useful for lower speed functions or exact timing functions
with infrequent actions.
Bit
$32 ($52)
Read/Write
Initial Value
MSB
R/W
7
0
R/W
6
0
R/W
5
0
R/W
4
0
R/W
3
0
R/W
2
0
R/W
1
0
LSB
R/W
0
0
TCNT0
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