ATtiny26 Atmel Corporation, ATtiny26 Datasheet - Page 73

• Manufacturer Part Number: ATtiny26
• Manufacturer: Atmel Corporation

Specifications of ATtiny26

• Flash (kbytes): 2 Kbytes
• Pin Count: 20
• Max. Operating Frequency: 16 MHz
• Cpu: 8-bit AVR
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 16
• Ext Interrupts: 11
• Usb Speed: No
• Usb Interface: No
• Spi: 1
• Twi (i2c): 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 11
• Adc Resolution (bits): 10
• Adc Speed (ksps): 15
• Analog Comparators: 1
• Resistive Touch Screen: No
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 0.12
• Eeprom (bytes): 128
• Self Program Memory: NO
• Dram Memory: No
• Nand Interface: No
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 2.7 to 5.5
• Operating Voltage (vcc): 2.7 to 5.5
• Fpu: No
• Mpu / Mmu: no / no
• Timers: 2
• Output Compare Channels: 3
• Pwm Channels: 4
• 32khz Rtc: No
• Calibrated Rc Oscillator: Yes

Timer/Counter1
Output Compare
RegisterB – OCR1B
Timer/Counter1
Output Compare
RegisterC – OCR1C
PLL Control and
Status Register –
PLLCSR
1477K–AVR–08/10
A compare match will set the compare interrupt flag OCF1A after a synchronization delay follow-
ing the compare event.
The Output Compare Register B is an 8-bit read/write register.
The Timer/Counter Output Compare Register B contains data to be continuously compared with
Timer/Counter1. Actions on compare matches are specified in TCCR1A. A compare match does
only occur if Timer/Counter1 counts to the OCR1B value. A software write that sets TCNT1 and
OCR1B to the same value does not generate a compare match.
A compare match will set the compare interrupt flag OCF1B after a synchronization delay follow-
ing the compare event.
The Output Compare Register C is an 8-bit read/write register.
The Timer/Counter Output Compare Register C contains data to be continuously compared with
Timer/Counter1. A compare match does only occur if Timer/Counter1 counts to the OCR1C
value. A software write that sets TCNT1 and OCR1C to the same value does not generate a
compare match.
If the CTC1 bit in TCCR1B is set, a compare match will clear TCNT1 and set an Overflow Inter-
rupt Flag (TOV1). The flag is set after a synchronization delay following the compare event.
This register has the same function in normal mode and PWM mode.
• Bit 7..3 – Res: Reserved Bits
These bits are reserved bits in the ATtiny26(L) and always read as zero.
• Bit 2 – PCKE: PCK Enable
The PCKE bit change the Timer/Counter1 clock source. When it is set, the asynchronous clock
mode is enabled and fast 64 MHz PCK clock is used as Timer/Counter1 clock source. If this bit
is cleared, the synchronous clock mode is enabled, and system clock CK is used as
Timer/Counter1 clock source. This bit can be set only if PLLE bit is set. It is safe to set this bit
only when the PLL is locked i.e., the PLOCK bit is 1.
• Bit 1 – PLLE: PLL Enable
When the PLLE is set, the PLL is started and if needed internal RC Oscillator is started as a PLL
reference clock. If PLL is selected as a system clock source the value for this bit is always 1.
• Bit 0 – PLOCK: PLL Lock Detector
Bit
$2C ($4C)
Read/Write
Initial Value
Bit
$2B ($4B)
Read/Write
Initial Value
Bit
$29 ($29)
Read/Write
Initial Value
MSB
MSB
R/W
R/W
R
7
0
7
0
7
–
0
R/W
R/W
R
6
0
6
0
6
–
0
R/W
R/W
R
5
0
5
0
5
–
0
R/W
R/W
R
4
0
4
0
4
–
0
R/W
R/W
R
3
0
3
0
3
–
0
PCKE
R/W
R/W
R/W
2
0
2
0
2
0
PLLE
R/W
R/W
R/W
0/1
1
0
1
0
1
PLOCK
LSB
LSB
R/W
R/W
R
0
0
0
0
0
0
PLLCSR
OCR1B
OCR1C
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