ATxmega64B3 Atmel Corporation, ATxmega64B3 Datasheet - Page 121

• Manufacturer Part Number: ATxmega64B3
• Manufacturer: Atmel Corporation

Specifications of ATxmega64B3

• Flash (kbytes): 64 Kbytes
• Pin Count: 64
• Max. Operating Frequency: 32 MHz
• Cpu: 8-bit AVR
• # Of Touch Channels: 16
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 36
• Ext Interrupts: 36
• Usb Transceiver: 1
• Usb Speed: Full Speed
• Usb Interface: Device
• Spi: 2
• Twi (i2c): 1
• Uart: 1
• Segment Lcd: 100
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 8
• Adc Resolution (bits): 12
• Adc Speed (ksps): 2000
• Analog Comparators: 2
• Resistive Touch Screen: No
• Temp. Sensor: Yes
• Crypto Engine: AES/DES
• Sram (kbytes): 4
• Eeprom (bytes): 2048
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: No
• Picopower: Yes
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.6 to 3.6
• Operating Voltage (vcc): 1.6 to 3.6
• Fpu: No
• Mpu / Mmu: no / no
• Timers: 2
• Output Compare Channels: 6
• Input Capture Channels: 6
• Pwm Channels: 6
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

11.4.1
11.4.2
8291A–AVR–10/11
NMI – Non-Maskable Interrupts
Interrupt Response Time
Which interrupts represent NMI and which represent regular interrupts cannot be selected. Non-
maskable interrupts must be enabled before they can be used. Refer to the device datasheet for
NMI present on each device.
An NMI will be executed regardless of the setting of the I bit, and it will never change the I bit. No
other interrupts can interrupt a NMI handler. If more than one NMI is requested at the same time,
priority is static according to the interrupt vector address, where the lowest address has highest
priority.
The interrupt response time for all the enabled interrupts is three CPU clock cycles, minimum;
one cycle to finish the ongoing instruction and two cycles to store the program counter to the
stack. After the program counter is pushed on the stack, the program vector for the interrupt is
executed. The jump to the interrupt handler takes three clock cycles.
If an interrupt occurs during execution of a multicycle instruction, this instruction is completed
before the interrupt is served. See
Figure 11-2 on page 122
Atmel AVR XMEGA B
for more details.
121