ATxmega64B3 Atmel Corporation, ATxmega64B3 Datasheet - Page 336

• Manufacturer Part Number: ATxmega64B3
• Manufacturer: Atmel Corporation

Specifications of ATxmega64B3

• Flash (kbytes): 64 Kbytes
• Pin Count: 64
• Max. Operating Frequency: 32 MHz
• Cpu: 8-bit AVR
• # Of Touch Channels: 16
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 36
• Ext Interrupts: 36
• Usb Transceiver: 1
• Usb Speed: Full Speed
• Usb Interface: Device
• Spi: 2
• Twi (i2c): 1
• Uart: 1
• Segment Lcd: 100
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 8
• Adc Resolution (bits): 12
• Adc Speed (ksps): 2000
• Analog Comparators: 2
• Resistive Touch Screen: No
• Temp. Sensor: Yes
• Crypto Engine: AES/DES
• Sram (kbytes): 4
• Eeprom (bytes): 2048
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: No
• Picopower: Yes
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.6 to 3.6
• Operating Voltage (vcc): 1.6 to 3.6
• Fpu: No
• Mpu / Mmu: no / no
• Timers: 2
• Output Compare Channels: 6
• Input Capture Channels: 6
• Pwm Channels: 6
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

25.15 Register Description
25.15.1
25.15.2
8291A–AVR–10/11
CTRLA – Control register A
CTRLB – ADC Control register B
• Bit 7:3 – Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always
write these bits to zero when this register is written.
• Bit 2 – CH0START: Channel Start Single Conversion
Setting this bit will start an ADC conversion. Bit is cleared by hardware when the conversion has
started. Writing this bit is equivalent to writing the START bits inside the ADC channel register.
• Bit 1 – FLUSH: Pipeline Flush
Setting this bit will flush the ADC. When this is done, the ADC clock is restarted on the next
peripheral clock edge, and the conversion in progress is aborted and lost.
After the flush and the ADC clock restart, the ADC will resume where it left off; i.e., if any conver-
sions were pending, these will enter the ADC and complete.
• Bit 0 – ENABLE: Enable
Setting this bit enables the ADC.
• Bit 7 – Reserved
This bit is unused and reserved for future use. For compatibility with future devices, always write
this bit to zero when this register is written.
• Bit 6:5 – CURRLIMIT[1:0]: Current Limitation
These bits can be used to limit the current consumption of the ADC by reducing the maximum
ADC sample rate. The available settings are shown in
current limitations are nominal values. Refer to the device datasheet for actual current limitation
for each setting.
Bit
+0x00
Read/Write
Initial Value
Bit
+0x01
Read/Write
Initial Value
–
ADC
R
7
–
R
7
–
0
0
R/W
CURRLIMIT[1:0]
6
0
R
6
–
0
R/W
5
0
R
5
–
0
CONVMODE
R/W
R
4
–
0
4
0
FREERUN
R/W
R
3
–
0
3
0
Atmel AVR XMEGA B
Table 25-1 on page
CH0START
R/W
R/W
RESOLUTION[1:0]
2
0
2
0
FLUSH
R/W
R/W
1
0
1
0
337. The indicated
ENABLE
R/W
R
0
0
0
–
0
CTRLA
CTRLB
336