ATxmega64B3 Atmel Corporation, ATxmega64B3 Datasheet - Page 280

• Manufacturer Part Number: ATxmega64B3
• Manufacturer: Atmel Corporation

Specifications of ATxmega64B3

• Flash (kbytes): 64 Kbytes
• Pin Count: 64
• Max. Operating Frequency: 32 MHz
• Cpu: 8-bit AVR
• # Of Touch Channels: 16
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 36
• Ext Interrupts: 36
• Usb Transceiver: 1
• Usb Speed: Full Speed
• Usb Interface: Device
• Spi: 2
• Twi (i2c): 1
• Uart: 1
• Segment Lcd: 100
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 8
• Adc Resolution (bits): 12
• Adc Speed (ksps): 2000
• Analog Comparators: 2
• Resistive Touch Screen: No
• Temp. Sensor: Yes
• Crypto Engine: AES/DES
• Sram (kbytes): 4
• Eeprom (bytes): 2048
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: No
• Picopower: Yes
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.6 to 3.6
• Operating Voltage (vcc): 1.6 to 3.6
• Fpu: No
• Mpu / Mmu: no / no
• Timers: 2
• Output Compare Channels: 6
• Input Capture Channels: 6
• Pwm Channels: 6
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

Figure 21-9. Fractional baud rate example.
21.10 USART in Master SPI Mode
21.11 USART SPI vs. SPI
8291A–AVR–10/11
baud clock
baud clock
Fractional
counter
counter
clk
Baud
Baud
Ideal
clk
PER
PER
Using the USART in master SPI mode requires the transmitter to be enabled. The receiver can
optionally be enabled to serve as the serial input. The XCK pin will be used as the transfer clock.
As for the USART, a data transfer is initiated by writing to the DATA register. This is the case for
both sending and receiving data, since the transmitter controls the transfer clock. The data writ-
ten to DATA are moved from the transmit buffer to the shift register when the shift register is
ready to send a new frame.
The transmitter and receiver interrupt flags and corresponding USART interrupts used in master
SPI mode are identical in function to their use in normal USART operation. The receiver error
status flags are not in use and are always read as zero.
Disabling of the USART transmitter or receiver in master SPI mode is identical to their disabling
in normal USART operation.
The USART in master SPI mode is fully compatible with the standalone SPI module in that:
When the USART is set in master SPI mode, configuration and use are in some cases different
from those of the standalone SPI module. In addition, the following differences exist:
• Timing diagrams are the same
• UCPHA bit functionality is identical to that of the SPI CPHA bit
• UDORD bit functionality is identical to that of the SPI DORD bit
• The USART transmitter in master SPI mode includes buffering, but the SPI module has no
• The USART receiver in master SPI mode includes an additional buffer level
• The USART in master SPI mode does not include the SPI write collision feature
• The USART in master SPI mode does not include the SPI double speed mode feature, but
transmit buffer
this can be achieved by configuring the baud rate generator accordingly
Atmel AVR XMEGA B
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